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symbios ? SYM53C895 pci to ultra2 scsi i/o processor with lvd link? universal transceivers order number s14030 technical manual december 1999 version 3.1
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic of?cer is prohibited. document db14-000112-00, december 1999 this document describes version 3.1 of lsi logic corporations symbios SYM53C895 pci to ultra2 scsi i/o processor with lvd link universal transceivers and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 1996C1999 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, symbios, symbios.com, and tolerant are registered trademarks of lsi logic corporation. scripts, and lvd link are trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies.
contents iii contents preface chapter 1 introduction 1.1 general description 1-1 1.1.1 new features in the SYM53C895 1-2 1.2 bene?ts of lvd link 1-3 1.3 bene?ts of ultra2 scsi 1-4 1.4 tolerant ? technology 1-4 1.5 SYM53C895 bene?ts summary 1-5 1.5.1 scsi performance 1-5 1.5.2 pci performance 1-6 1.5.3 integration 1-7 1.5.4 ease of use 1-7 1.5.5 flexibility 1-8 1.5.6 reliability 1-9 1.5.7 testability 1-9 chapter 2 functional description 2.1 scsi core 2-2 2.2 dma core 2-2 2.2.1 dma fifo 2-3 2.3 scripts processor 2-7 2.3.1 internal scripts ram 2-8 2.4 prefetching scripts instructions 2-8 2.4.1 op code fetch burst capability 2-9 2.5 designing an ultra2 scsi system 2-10 2.5.1 using the scsi clock quadrupler 2-11 2.6 SYM53C895 interfaces 2-11 2.6.1 parallel rom interface 2-11
iv contents 2.6.2 serial eeprom interface 2-13 2.6.3 scsi bus interface 2-15 2.7 SYM53C895 modes 2-20 2.7.1 pci cache mode 2-20 2.7.2 big and little endian modes 2-20 2.7.3 loopback mode 2-22 2.8 parity options 2-22 2.8.1 scsi termination 2-24 2.8.2 system engineering note 2-25 2.8.3 (re)select during (re)selection 2-28 2.9 synchronous operation 2-28 2.9.1 determining the data transfer rate 2-29 2.9.2 ultra2 scsi synchronous data transfers 2-29 2.10 interrupt handling 2-32 2.10.1 polling and hardware interrupts 2-32 2.10.2 registers 2-32 2.10.3 fatal vs. nonfatal interrupts 2-34 2.10.4 masking 2-35 2.10.5 stacked interrupts 2-36 2.10.6 halting in an orderly fashion 2-37 2.10.7 sample interrupt service routine 2-38 2.11 chained block moves 2-39 2.11.1 wide scsi send bit (wss) 2-40 2.11.2 wide scsi receive bit (wsr) 2-40 2.11.3 scsi wide residue (swide) register 2-40 2.11.4 scsi output data latch (sodl) register 2-41 2.11.5 chained block move scripts instruction 2-41 chapter 3 pci functional description 3.1 pci addressing 3-1 3.2 pci bus commands and functions supported 3-2 3.3 pci cache mode 3-4 3.3.1 support for pci cache line size register 3-4 3.3.2 selection of cache line size 3-4 3.3.3 alignment 3-4 3.3.4 memory move misalignment 3-5 3.3.5 memory write and invalidate command 3-6
contents v 3.3.6 memory read multiple command 3-9 3.4 con?guration registers 3-10 chapter 4 signal descriptions 4.1 voltage capabilities and limitations 4-3 4.2 internal pull-ups on SYM53C895 pins 4-4 4.3 pin descriptions 4-5 chapter 5 registers 5.1 pci con?guration registers 5-1 5.2 scsi registers 5-15 chapter 6 scsi scripts instruction set 6.1 low-level register interface mode 6-2 6.2 high-level scsi scripts mode 6-2 6.2.1 sample operation 6-3 6.3 block move instruction 6-6 6.3.1 first dword 6-6 6.3.2 second dword 6-12 6.4 i/o instruction 6-13 6.4.1 first dword 6-13 6.4.2 second dword 6-21 6.5 read/write instructions 6-22 6.5.1 first dword 6-22 6.5.2 second dword 6-23 6.5.3 read-modify-write cycles 6-23 6.5.4 move to/from sfbr cycles 6-24 6.6 transfer control instruction 6-26 6.6.1 first dword 6-26 6.6.2 second dword 6-32 6.7 memory move instructions 6-33 6.7.1 first dword 6-34 6.7.2 read/write system memory from a script 6-34 6.7.3 second dword 6-35 6.7.4 third dword 6-35 6.8 load and store instructions 6-36 6.8.1 first dword 6-37
vi contents 6.8.2 second dword 6-38 6.8.3 third dword 6-38 chapter 7 electrical characteristics 7.1 dc characteristics 7-1 7.2 3.3 volt pci dc characteristics 7-6 7.3 tolerant technology electrical characteristics 7-8 7.4 ac characteristics 7-11 7.5 pci and external memory interface timing diagram 7-14 7.5.1 timing diagrams included in this section 7-15 7.6 scsi timings 7-51 appendix a register summary appendix b external memory interface diagram examples appendix c circuit board layout issues c.1 signal separation c-2 c.2 routing signal lines c-2 c.3 impedance matching c-2 c.4 termination and stub length c-2 c.5 decoupling c-3 c.6 dielectric c-3 c.7 considerations speci?c to the SYM53C895 c-3 c.7.1 rbias +/ - pins c-3 c.7.2 physical dimensions c-4 c.7.3 power requirements c-4 c.7.4 v dd-a pin c-4 c.7.5 terminators c-4 c.7.6 capacitive load c-5 c.7.7 spi-2 document c-5 index customer feedback
contents vii figures 1.1 SYM53C895 chip block diagram 1-2 2.1 dma fifo sections 2-3 2.2 SYM53C895 host interface scsi datapath 2-7 2.3 8-bit high voltage differential wiring diagram for ultra2 scsi 2-19 2.4 regulated termination for ultra2 scsi 2-25 2.5 determining the synchronous transfer rate 2-31 2.6 block move and chained block move instructions 2-39 4.1 SYM53C895 functional signal grouping 4-2 6.1 scripts overview 6-5 7.1 lvd transmitter 7-3 7.2 lvd receiver 7-3 7.3 rise and fall time test conditions 7-9 7.4 input filtering 7-9 7.5 hysteresis of scsi receiver 7-10 7.6 input current as a function of input voltage 7-10 7.7 output current as a function of output voltage 7-11 7.8 external clock timing 7-12 7.9 reset input 7-13 7.10 interrupt output 7-14 7.11 pci con?guration register read 7-16 7.12 pci con?guration register write 7-17 7.13 operating register/scripts ram read 7-18 7.14 operating register/scripts ram write 7-19 7.15 external memory read 7-21 7.16 external memory write 7-24 7.17 op code fetch, nonburst 7-27 7.18 burst op code fetch 7-29 7.19 back-to-back read 7-31 7.20 back-to-back write 7-33 7.21 burst read 7-35 7.22 burst write 7-37 7.23 read cycle, normal/fast memory ( 3 128 kbytes), single byte access 7-39 7.24 normal/fast memory ( 3 128 kbytes), single byte access, write cycle, 7-40
viii contents 7.25 normal/fast memory ( 3 128 kbytes), multiple byte access, read cycle 7-42 7.26 normal/fast memory ( 3 128 kbytes) multiple byte access, write cycle 7-44 7.27 read cycle, slow memory ( 3 128 kbytes) 7-46 7.28 write cycle, slow memory ( 3 128 kbytes) 7-47 7.29 read cycle, 64 kbytes rom 7-49 7.30 write cycle, 64 kbytes rom 7-50 7.31 initiator asynchronous send 7-51 7.32 initiator asynchronous receive 7-52 7.33 target asynchronous send 7-52 7.34 target asynchronous receive 7-53 7.35 initiator and target synchronous transfers 7-53 7.36 SYM53C895 pin diagram, 272-ball bga (top view) 7-60 7.37 SYM53C895 pin diagram, 208-pin qfp 7-63 7.38 SYM53C895 mechanical drawing, 208-pin qfp 7-66 7.39 SYM53C895 mechanical drawing, 272 bga 7-68 b.1 16 kbytes interface with 200 ns memory b-1 b.2 64 kbytes interface with 200 ns memory b-2 b.3 256 kbytes interface with 150 ns memory b-3 b.4 512 kbytes interface with 150 ns memory b-4 tables 2.1 external memory support 2-12 2.2 mode a serial eeprom data format 2-14 2.3 mode c serial eeprom data format 2-15 2.4 high voltage differential operation 2-17 2.5 bits used for parity control and generation 2-22 2.6 scsi parity control 2-23 2.7 scsi parity errors and interrupts 2-24 2.8 transmission mode 2-25 3.1 pci bus commands supported 3-3 4.1 SYM53C895 internal pull-ups 4-4 4.2 SYM53C895 power and ground pins 4-5 4.3 system pins 4-7 4.4 address and data pins 4-7 4.5 interface control pins 4-8 4.6 arbitration pins 4-9
contents ix 4.7 error reporting pins 4-9 4.8 scsi pins, lvd link mode 4-10 4.9 scsi pins, single-ended mode 4-12 4.10 scsi pins, high voltage differential mode 4-14 4.11 additional pins 4-16 4.12 external memory interface pins 4-18 5.1 pci con?guration register map 5-2 5.2 scsi register map 5-16 5.3 synchronous clock conversion factor 5-26 5.4 asynchronous clock conversion factor 5-27 5.5 examples of synchronous transfer periods and rates for scsi-1 5-30 5.6 example synchronous transfer periods and rates for fast scsi, ultra scsi, and ultra2 scsi 5-31 5.7 maximum synchronous offset 5-31 5.8 timeout periods 5-76 5.9 timeout periods, 50 mhz clock 5-78 5.10 timeout periods, 40/160 mhz clock 5-79 5.11 diffsens voltage levels and scsi operating modes 5-89 6.1 scripts instructions 6-3 6.2 scsi information transfer phase 6-11 6.3 read/write instructions 6-24 6.4 transfer control instructions 6-26 6.5 scsi phase comparisons 6-29 7.1 absolute maximum stress ratings 7-1 7.2 operating conditions 7-2 7.3 scsi signals, low voltage differential drivers - sd[15:0]+/ - , sdp[1:0]+/ - , sreq+/ - , sack+/ - , smsg+/ - , sio+/ - , scd+/ - , satn+/ - , sbsy+/ - , ssel+/ - , srst+/ - * 7-2 7.4 scsi signals, low voltage differential receivers - sd[15:0]+/ - , sdp[1:0]+/ - , sreq+/ - , sack+/ - , smsg+/ - , sio+/ - , scd+/ - , satn+ - , sbsy+/ - , ssel+/ - , srst+/ - 7-3 7.5 scsi signal - diffsens 7-3 7.6 scsi signals - rbias+/ - 7-4 7.7 capacitance 7-4 7.8 output signal - mac/_testout 7-4
x contents 7.9 input signals - clk, rst/ 1 , idsel, gnt/, sclk/ 7-4 7.10 bidirectional signals - ad[31:0], c_be/[3:0], frame/, irdy/, trdy/, devsel/, stop/, perr/, par, req/ irq/, serr/ 7-5 7.11 bidirectional signals - gpio0_fetch/, gpio1_master/, gpio2, gpio3, gpio4, mad[7:0] 7-5 7.12 bidirectional signals - mas/[1:0], mce/, moe/, mwe/ 7-5 7.13 input signal - big_lit/ 7-6 7.14 bidirectional signals - ad[31:0], c_be[3:0]/, frame/, irdy/, trdy/, devsel/, stop/, perr/, par, bytepar[3:0] 7-6 7.15 input signals - clk, gnt/, idsel, rst/ 7-6 7.16 output signals - irq/, req/ 7-7 7.17 output signal - serr/ 7-7 7.18 tolerant technology electrical characteristics 7-8 7.19 external clock timing 7-11 7.20 reset input 7-13 7.21 interrupt output 7-14 7.22 con?guration register read timings 7-16 7.23 con?guration register write timings 7-17 7.24 operating register/scripts ram read timings 7-18 7.25 operating register/scripts ram write timings 7-19 7.26 external memory read timings 7-20 7.27 external memory write timings 7-23 7.28 op code fetch, nonburst timings 7-26 7.29 burst op code fetch timings 7-28 7.30 back to back read timings 7-30 7.31 back to back write timings 7-32 7.32 burst read timings 7-34 7.33 burst write timings 7-36 7.34 read cycle timings, normal/fast memory ( 3 128 kbytes), single byte access 7-38 7.35 write cycle timings, normal/fast memory ( 3 128 kbytes), single byte access 7-40 7.36 read cycle timings, slow memory ( 3 128 kbytes) 7-46 7.37 write cycle timings, slow memory ( 3 128 kbytes) 7-47 7.38 read cycle timings, 64 kbytes rom 7-49 7.39 write cycle timings, 64 kbytes rom 7-50
contents xi 7.40 initiator asynchronous send 7-51 7.41 initiator asynchronous receive 7-52 7.42 target asynchronous send 7-52 7.43 target asynchronous receive 7-53 7.44 scsi-1 transfers (single-ended, 5.0 mbytes/s) 7-54 7.45 scsi-1 transfers (differential, 4.17 mbytes/s) 7-54 7.46 scsi-2 fast transfers 10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 40 mhz clock 7-55 7.47 scsi-2 fast transfers 10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 50 mhz clock 7-56 7.48 ultra scsi single-ended transfers 20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers), quadrupled 40 mhz clock 7-57 7.49 ultra scsi high voltage differential transfers 20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers), 80 mhz clock1 7-58 7.50 ultra2 scsi transfers 40.0 mbytes/s (8-bit transfers) or 80.0 mbytes/s (16-bit transfers), quadrupled 40 mhz clock 7-59 7.51 bga position and signal name alphabetically 7-61 7.52 bga position numerically and signal name 7-62 7.53 signal name by pin number qfp 7-64 7.54 alphabetical signal name and pin number qfp 7-65 a.1 sym53c896 register map a-1
xii contents
preface xiii preface this book is the primary reference and technical manual for the lsi logic symbios ? SYM53C895 pci to ultra2 scsi i/o processor with lvd link? universal transceivers. it contains a complete functional description for the product and includes complete physical and electrical speci?cations. this data manual assumes the user is familiar with the current and proposed standards for scsi and pci. for additional background information on these topics, please refer to the list of reference materials provided below. audience this document was prepared for system designers and programmers who are using this device to design an ultra2 scsi port for pci-based personal computers, workstations, servers, or embedded applications. organization chapter 1, introduction , contains the general description about the SYM53C895 pci to ultra2 scsi i/o processor. chapter 2, functional description , contains details about the three functional blocks: the scsi core, the dma core, and the scripts processor. chapter 3, pci functional description , contains the pci bus commands, and functions supported. chapter 4, signal descriptions , contains information about the signal de?nitions using tables and illustrations. chapter 5, registers , contains descriptions of the pci registers and the SYM53C895 operating registers.
xiv preface chapter 6, scsi scripts instruction set , contains detailed information about utilitizing scsi scripts mode. chapter 7, electrical characteristics , contains information pertaining to dc and ac characteristics for the SYM53C895 device. appendix a, register summary , contains a quick reference to the registers used for the SYM53C895 device. appendix b, external memory interface diagram examples , contains four diagram examples pertaining to the interface of the external memory. appendix c, circuit board layout issues , provides details concerning signals and other considerations speci?c to the SYM53C895. related publications for background information, please contact: ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 ask for document number x3.131-1994 (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 7956 (outside u.s.) fax (303) 397-2740 ask for document number x3.131-1994 (scsi-2) or x3.253 (scsi-3 parallel interface) endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor
preface xv prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 ask for document number isbn 0-13-796855-8, scsi: understanding the small computer system interface lsi logic (storage components) electronic bulletin board (719) 533-7235 ask for document symbios ? sym53c8xx pci-scsi i/o processors programming guide , order number j25972i scsi electronic bulletin board (719) 533-7950 lsi logic internet anonymous ftp site ftp.symbios.com (204.131.200.1) directory: /pub/symchips/scsi lsi logic world wide web home page www.lsilogic.com pci special interest group pci local bus speci?cation, revision 2.1 2575 n.e. katherine hillsboro, or 97214 (800) 433-5177; (503) 693-6232 (international); fax (503) 693-8344 conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x for example, 0x32cf. binary numbers are indicated by the pre?x 0b for example, 0b0011.0010.1100.1111.
xvi preface revision history page no. date revision/remarks n/a 7/96 ver. 1.0 1-2, 2-5, 2-17, 2-19, 3-11, 3-12, 4-2, 4-4, 4-7, 4-8, 4-9, 4-10, 4-11, 4-13, 5-39, 5-40, 7-2, 7-3, 7-7, 7-8, 7-38, 7-42, 7-44 1/97 ver. 2.0. added serial eeprom interface; changed operation of parallel eprom interface; added information on ultra2 scsi termination; added lvd electrical speci?cations and ultra2 scsi timings; added pci con?guration registers for subsystem id and subsystem vendor id; pinout/pin numbering corrections. 2-16 - 2-17, 4-3 - 4-6, 4-11, 4-22, 7-1, 7-2, 7-4 - 7-5, d[ 1:4 ] 9/98 ver. 3.0. merged addendum; merged sen892 (diffsens) in chapter 2; chapter 3 - added 292-bga ?gure/tables and updated mad[3:1] signals;chapter 7 - substituted source and sink values, and changed other values. merged sen893 and sen898 into appendix d. all 12/99 ver. 3.1. lsi logic formats applied. changes to chapter 4 regarding pbga from 292 to 272. updated chapter 6, scsi scripts with current information.
symbios SYM53C895 pci to ultra2 scsi i/o processor 1-1 chapter 1 introduction this chapter provides a general overview on the SYM53C895 pci to ultra2 scsi i/o processor and other members of the sym53c8xx family of pci to scsi i/o processors. this chapter contains these topics: section 1.1, general description, page 1-1 section 1.2, bene?ts of lvd link, page 1-3 section 1.3, bene?ts of ultra2 scsi, page 1-4 section 1.4, tolerant? technology, page 1-4 section 1.5, SYM53C895 bene?ts summary, page 1-5 1.1 general description the SYM53C895 pci to scsi i/o processor brings ultra2 scsi performance to host adapter, workstation, and general computer designs, making it easy to add a high-performance scsi bus to any pci system. it supports ultra2 scsi transfer rates and allows you to increase scsi connectivity and cable length with low voltage differential (lvd) signaling for scsi. the SYM53C895 has a local memory bus for local storage of the device bios rom in ?ash memory or standard eeproms. the SYM53C895 supports big and little endian byte addressing to accommodate a variety of data con?gurations. the SYM53C895 supports programming of local ?ash memory for updates to bios or scripts? programs. the chip is packaged in a 208-pin quad ?at pack or a 272-ball bga. system diagrams showing the connections of the SYM53C895 with an external rom or ?ash memory are pictured in appendix b . a block diagram of the SYM53C895 is pictured in figure 1.1 on page 1-2 .
1-2 introduction figure 1.1 SYM53C895 chip block diagram symbios lvd link technology is the lsi logic implementation of low voltage differential (lvd). lvd link transceivers allow the SYM53C895 to perform single-ended and lvd transfers, and support external high voltage differential transceivers. the SYM53C895 integrates a high performance scsi core, a pci bus master dma core, and the symbios scsi scripts processor to meet the ?exibility requirements of scsi-3 and ultra2 scsi standards. it is designed to implement multithreaded i/o algorithms with a minimum of processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. 1.1.1 new features in the SYM53C895 the SYM53C895 is functionally similar to the sym53c875 pci to scsi i/o processor, with added support for ultra2 scsi. some software enhancements, and use of lvd, enable the SYM53C895 to transfer data at ultra2 scsi transfer rates. most of the feature enhancements in the SYM53C895 are included to enable the chip to take advantage of ultra2 scsi transfer rates. scsi clock quadrupler pci master and slave control block memory control data fifo 112 or 816 bytes scsi scripts processor operating registers con?g registers scripts ram local memory bus scsi fifo and scsi control block lvd link transceivers tolerant drivers and receivers pci external memory scsi bus
bene?ts of lvd link 1-3 optional 816-byte dma fifo supports large block transfers at ultra2 scsi speeds. the default fifo size is 112 bytes. thirty-one levels of scsi synchronous offset increases the pace of synchronous transfers to match ultra2 scsi transfer speeds. on-chip lvd link transceivers allow increased connectivity, longer cable length, and improved performance. they also automatically sense the type of device connected to the scsi bus and switch as needed to single-ended, lvd, or high voltage differential mode (if the chip is connected to external transceivers). on-chip scsi clock quadrupler can achieve 160 mhz frequency with an external 40 mhz oscillator. supports subsystem id and subsystem vendor id registers in pci con?guration space. support for serial eeprom interface. 1.2 bene?ts of lvd link the SYM53C895 supports low voltage differential (lvd) for scsi, a signaling technology that increases the reliability of scsi data transfers over longer distances than supported by single-ended (se) scsi. the low current output of lvd allows the i/o transceivers to be integrated directly onto the chip. lvd provides the reliability of high voltage differential scsi without the added cost of external differential transceivers. ultra2 scsi with lvd allows a longer scsi cable and more devices on the bus, using the same cables de?ned in the scsi-3 parallel interface standard for ultra scsi. lvd provides a long-term migration path to even faster scsi transfer rates without compromising signal integrity, cable length, or connectivity. for backward compatibility to existing se devices, the SYM53C895 features universal lvd link transceivers that can switch between lvd and se scsi modes. the lvd link technology also supports high-power differential signaling in legacy systems when external transceivers are connected to the SYM53C895. this allows the SYM53C895 to be used in both legacy and ultra2 scsi applications.
1-4 introduction 1.3 bene?ts of ultra2 scsi ultra2 scsi is an extension of the spi-2 draft standard that allows faster synchronous scsi transfer rates and de?nes a new physical layer, lvd scsi. lvd scsi provides an incremental evolution from scsi-2 and ultra scsi. when enabled, ultra2 scsi performs 40 mega transfers per second, which results in approximately double the synchronous transfer rates of ultra scsi. the SYM53C895 can perform 16 bit, ultra2 scsi synchronous transfers as fast as 80 mbytes/s. this advantage is most noticeable in heavily loaded systems or large-block size applications such as video on-demand and image processing. one advantage of ultra2 scsi is that it signi?cantly improves scsi bandwidth while preserving existing hardware and software investments. the primary software changes enable the chip to perform synchronous negotiations for ultra2 scsi rates, and to enable the clock quadrupler. ultra2 scsi uses the same connectors as ultra scsi, but can operate with longer cables and more devices on the bus. chapter 2 contains more information on migrating from an ultra scsi design to support ultra2 scsi. 1.4 tolerant ? technology the SYM53C895 features tolerant technology, which includes active negation on the scsi drivers and input signal ?ltering on the scsi receivers. active negation drives the scsi request, acknowledge, data, and parity signals active high rather than allowing them to be passively pulled up by terminators. active negation is enabled by setting bit 7 in the stest3 register. tolerant receiver technology improves data integrity in unreliable cabling environments, where other devices would be subject to data corruption. tolerant receivers ?lter the scsi bus signals to eliminate unwanted transitions without the long signal delay associated with rc-type input ?lters. this improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with scsi operations. tolerant input signal ?ltering is a built in feature of the
SYM53C895 bene?ts summary 1-5 SYM53C895 and all symbios fast scsi, ultra scsi, and ultra2 scsi devices. on the SYM53C895, the user can select a ?ltering period of 30 or 60 ns, with bit 1 in the stest2 register. the bene?ts of tolerant include increased immunity to noise when the signal is going high, better performance due to balanced duty cycles, and improved fast scsi transfer rates. in addition, tolerant scsi devices do not cause glitches on the scsi bus at power up or power down, so other devices on the bus are also protected from data corruption. when it is used with the lvd link transceivers, tolerant provides excellent signal quality and data reliability in real world cabling environments. tolerant is compatible with both the alternative one and alternative two termination schemes proposed by the american national standards institute. 1.5 SYM53C895 bene?ts summary this section provides an overview of the SYM53C895 bene?ts and features. it includes these topics: scsi performance pci performance integration ease of use flexibility reliability testability 1.5.1 scsi performance to improve scsi performance, the SYM53C895: has integrated lvd link universal transceivers which: C support se, lvd, and high voltage differential signals (with external transceivers) C allow greater device connectivity and longer cable length
1-6 introduction C lvd link transceivers save the cost of external differential transceivers C support a long-term performance migration path bursts up to 512 bytes across the pci bus through its 816 byte fifo performs wide ultra2 scsi synchronous transfers as fast as 80 mbytes/s includes an on-chip scsi clock quadrupler that allows the chip to achieve ultra2 scsi transfer rates with a 40 mhz clock includes 4 kbytes internal ram for scripts instruction storage has 31 levels of scsi synchronous offset supports variable block size and scatter/gather data transfers. performs sustained memory-to-memory dma transfers faster than 47 mbytes/s (@ 33 mhz) minimizes scsi i/o start latency performs complex bus sequences without interrupts, including restore data pointers reduces isr overhead through a unique interrupt status reporting method includes load and store scripts instructions to increase performance of data transfers to and from chip registers supports target disconnect and later reconnect with no interrupt to the system processor supports multithreaded i/o algorithms in scsi scripts with fast i/o context switching supports expanded register move instructions for additional arithmetic capability 1.5.2 pci performance to improve pci performance, the SYM53C895: complies with pci 2.1 speci?cation supports 32-bit 33 mhz pci interface bursts 2, 4, 8, 16, 32, 64, or 128 dwords across the pci bus
SYM53C895 bene?ts summary 1-7 supports 32-bit word data bursts with variable burst lengths prefetches up to 8 dwords of scripts instructions bursts scripts op code fetches across the pci bus performs zero wait-state bus master data bursts faster than 110 mbytes/s (@ 33 mhz) supports pci cache line size register supports pci write and invalidate, read line, and read multiple commands 1.5.3 integration the SYM53C895 contains these integration features: integrated lvd transceivers full 32-bit pci dma bus master memory to memory move instructions to allow use as a third-party pci bus dma controller. high performance scsi core integrated scripts processor 1.5.4 ease of use the SYM53C895 provides ease of use by having: up to one megabyte of add-in memory support for bios and scripts storage direct pci to scsi connection reduced scsi development effort compiler-compatible with existing sym53c7xx and sym53c8xx family scripts direct connection to pci, and scsi single-ended and differential buses development tools and sample scsi scripts available maskable and pollable interrupts wide scsi, a or p cable, and up to 16 devices supported
1-8 introduction three programmable scsi timers: select/reselect, handshake-to- handshake, and general purpose. the timeout period is programmable from 100 m s to greater than 25.6 seconds software for pc-based operating system support support for relative jumps scsi selected as id bits for responding with multiple ids 1.5.5 flexibility the SYM53C895 contains these ?exibility features: universal lvd transceivers that are backward compatible with single- ended or high-power differential devices high level programming interface (scsi scripts) programs local memory bus ?ash memory big/little endian support selectable 112 or 816 byte dma fifo for backward compatibility tailored scsi sequences execute from main system ram or internal scripts ram flexible programming interface to tune i/o performance or to adapt to unique scsi devices support for changes in the logical i/o interface de?nition low level access to all registers and all scsi bus signals fetch, master, and memory access control pins separate scsi and system clocks scsi clock quadrupler bits enable ultra2 scsi transfer rates with a 40 mhz scsi clock selectable irq pin disable bit ability to route system clock to scsi clock
SYM53C895 bene?ts summary 1-9 1.5.6 reliability the SYM53C895 contains these reliability features: 2 kv esd protection on scsi signals protection against bus re?ections due to impedance mismatches controlled bus assertion times (reduces rfi, improves reliability, and eases fcc certi?cation) latch-up protection greater than 150 ma voltage feed through protection (minimum leakage current through scsi pads) more than 25% of pins are power and ground power and ground isolation of i/o pads and internal chip logic tolerant technology provides: C active negation of scsi data, parity, request, and acknowledge signals for improved fast scsi transfer rates C input signal ?ltering on scsi receivers improves data integrity, even in noisy cabling environments 1.5.7 testability the SYM53C895 contains these testability features: all scsi signals accessible through programmed i/o scsi loopback diagnostics scsi bus signal continuity checking support for single-step mode operation test mode (and tree) to check pin continuity to the board
1-10 introduction
symbios SYM53C895 pci to ultra2 scsi i/o processor 2-1 chapter 2 functional description this chapter provides information about three functional blocks for the SYM53C895 processor: scsi core, dma core, and scripts processor. other topics include speci?c interfaces, modes, and various options. chapter 2 contains these sections: section 2.1, scsi core, page 2-2 section 2.2, dma core, page 2-2 section 2.3, scripts processor, page 2-7 section 2.4, prefetching scripts instructions, page 2-8 section 2.5, designing an ultra2 scsi system, page 2-10 section 2.6, SYM53C895 interfaces, page 2-11 section 2.7, SYM53C895 modes, page 2-20 section 2.8, parity options, page 2-22 section 2.9, synchronous operation, page 2-28 section 2.10, interrupt handling, page 2-32 section 2.11, chained block moves, page 2-39 note that lsi logic supplies software that supports the SYM53C895 and the entire symbios product line of scsi processors and controllers.
2-2 functional description 2.1 scsi core the scsi core supports an 8-bit or 16-bit data bus. it supports ultra2 scsi synchronous transfer rates up to 80 mbytes/s on a 16-bit, lvd scsi bus. the scsi core can be programmed with scsi scripts, making it easy to ?ne tune the system for speci?c mass storage devices or scsi-3 requirements. the scsi core offers low-level register access or a high-level control interface. like ?rst generation scsi devices, the SYM53C895 scsi core can be accessed as a register-oriented device. the ability to sample and/or assert any signal on the scsi bus is useful for error recovery and diagnostic procedures. in support of loopback diagnostics, the scsi core could perform a self-selection and operate as both an initiator and a target. the integrated scripts processor controls the SYM53C895 scsi core through a high-level logical interface. commands controlling the scsi core are fetched out of the main host memory or local memory. these commands instruct the scsi core to transfer information, change bus phases and, in general, implement all aspects of the scsi protocol. the scripts processor is a special high-speed processor optimized for scsi protocol. 2.2 dma core the dma core is a bus master dma device that attaches directly to the industry standard pci bus. the dma core is tightly coupled to the scsi core through the scripts processor, which supports uninterrupted scatter/gather memory operations. the SYM53C895 supports 32-bit memory and automatically supports misaligned dma transfers. a 112 or 816 byte fifo allows the SYM53C895 to support 2, 4, 8, 16, 32, 64, or 128 dword bursts across the pci bus interface.
dma core 2-3 2.2.1 dma fifo the dma fifo is 4-bytes wide and 28 or 204 transfers deep. the dma fifo is illustrated in figure 2.1 . to assure compatibility with older products in the sym53c8xx family, the user may set the dma fifo size to 112 bytes by clearing the dma fifo size bit, bit 5 in the chip test five (ctest5) register. the 816-byte fifo size is related to the SYM53C895 fifo architecture. it does not re?ect any speci?c system design parameters or expectations. figure 2.1 dma fifo sections 2.2.1.1 data paths the data path through the SYM53C895 is dependent on whether data is being moved into or out of the chip. it also depends on whether scsi data is being transferred asynchronously or synchronously. 32 bits wide 28 or 204 transfers deep 8 bits byte lane 3 8 bits byte lane 2 8 bits byte lane 1 8 bits byte lane 0
2-4 functional description figure 2.2 shows how data is moved to/from the scsi bus in each of the different modes. to determine if any bytes remain in the data path when the chip halts an operation, follow the detailed instructions in the next sections. asynchronous scsi send C follow these steps for asynchronous scsi send operations: step 1. to calculate dma fifo size: if the dma fifo size is set to 112 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least signi?cant bits of the dbc register from the 7-bit value of the dfifo register. and the result with 0x7f for a byte count between zero and 112. if the dma fifo size is set to 816 bytes (using bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?cant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the ctest5 register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between 0 and 816. step 2. to determine if any bytes are left in the scsi output data latch (sodl) register, read bit 5 in the scsi status zero (sstat0) and scsi status two (sstat2) registers. if bit 5 is set in the sstat0 or sstat2, then the least signi?cant byte or the most signi?cant byte in the sodl register is full, respectively. checking this bit also reveals bytes left in the sodl register from a chained move operation with an odd byte count. synchronous scsi send C follow these steps for synchronous scsi send: step 1. to calculate dma fifo size: if the dma fifo size is set to 112 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation,
dma core 2-5 subtract the seven least signi?cant bits of the dbc register from the 7-bit value of the dfifo register. and the result with 0x7f for a byte count between zero and 112. if the dma fifo size is set to 816 bytes (using bit 5 of the ctest5 register), subtract the 10 least signi?cant bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the ctest5 register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between 0 and 816. step 2. to determine if any bytes are left in the scsi output data latch (sodl) register, read bit 5 in the scsi status zero (sstat0) and scsi status two (sstat2) registers. if bit 5 is set in the sstat0 or sstat2, then the least signi?cant byte or the most signi?cant byte in the sodl register is full, respectively. checking this bit also reveals bytes left in the sodl register from a chained move operation with an odd byte count. step 3. to determine if any bytes are left in the sodr register (a hidden buffer register which is not accessible), read bit 6 in the sstat0 and sstat2 registers. if bit 6 is set in the sstat0 or sstat2, then the least signi?cant byte or the most signi?cant byte in the sodr register is full. asynchronous scsi receive C follow these steps for asynchronous scsi receive: step 1. to calculate dma fifo size: if the dma fifo size is set to 112 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least signi?cant bits of the dbc register from the 7-bit value of the dfifo register. and the result with 0x7f for a byte count between 0 and 112. if the dma fifo size is set to 816 bytes (using bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?cant bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the ctest5 register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between 0 and 816.
2-6 functional description step 2. to determine if any bytes are left in the scsi input data latch (sidl) register, read bit 7 in the sstat0 and sstat2 register. if bit 7 is set in the sstat0 or sstat2, then the least signi?cant byte or the most signi?cant byte is full. step 3. to determine whether a byte is left in the scsi wide residue (swide) register, read the wide scsi receive bit (scsi control two (scntl2), bit 0) synchronous scsi receive. this applies toward any wide transfers that have been performed using the chained move instruction, follow these steps for synchronous scsi receive: step 1. to calculate dma fifo size: if the dma fifo size is set to 112 bytes, subtract the seven least signi?cant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with 0x7f for a byte count between 0 and 112. if the dma fifo size is set to 816 bytes (using bit 5 of the chip test five (ctest5 register), subtract the 10 least signi?cant bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits 1-0 in the ctest5 register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between 0 and 816. step 2. read bits [7:4] of the scsi status one (sstat1) register and bit 4 of the scsi status two (sstat2) register, the binary representation of the number of valid bytes in the scsi fifo, to determine if any bytes are left in the scsi fifo. step 3. to determine whether a byte is left in the scsi wide residue (swide) register, read the wide scsi receive bit (scsi control two (scntl2, bit 0) SYM53C895 host interface data paths. this applies toward any wide transfers that have been performed using the chained move instruction.
scripts processor 2-7 figure 2.2 SYM53C895 host interface scsi datapath 2.3 scripts processor the scsi scripts processor allows both dma and scsi commands to be fetched from host memory or internal scripts ram. algorithms written in scsi scripts control the actions of the scsi and dma cores and are executed from 32-bit system ram or internal scripts ram. the scripts processor executes complex scsi bus sequences independently of the host cpu. the scripts processor can begin a scsi i/o operation in approximately 500 ns. algorithms may be designed to tune scsi bus performance to adjust to new bus device types (such as scanners, communication gateways, etc.), or to incorporate changes in the scsi-2 or scsi-3 logical bus de?nitions without sacri?cing i/o performance. scsi scripts are hardware independent, so they can be used interchangeably on any host or cpu system bus. pci interface dma fifo (32 bits 28 sodl register scsi interface swide register or 204) pci interface dma fifo (32 bits 28 or 204) sidl register scsi interface swide register pci interface dma fifo (32 bits 28 or 204) sidl register scsi interface pci interface dma fifo (32 bits 28 sodl register sodr interface or 204) scsi interface asynchronous scsi send asynchronous scsi receive synchronous scsi send synchronous scsi receive
2-8 functional description 2.3.1 internal scripts ram the SYM53C895 has 4 kbytes (1024 x 32 bits) of internal, general purpose ram. the ram is designed for scripts program storage, but is not limited to this type of information. when the chip fetches scripts instructions or table indirect information from the internal ram, these fetches remain internal to the chip and do not use the pci bus. other types of access to the ram by the SYM53C895 use the pci bus as if they were external accesses. the mad5 pin enables the 4 kbytes internal ram, when it is connected to v dd through a 4.7 k w resistor. to disable the internal ram, connect a 4.7 k w resistor between the mad5 pin and v ss . the pci system bios can relocate the ram anywhere in a 32-bit address space. the ram base address register in pci con?guration space contains the base address of the internal ram. this register is similar to the rom base address register in pci con?guration space. to simplify loading of scripts instructions, the base address of the ram appears in the scratchb register when bit 3 of the ctest2 register is set. the ram is byte-accessible from the pci bus and is visible to any bus-mastering device on the bus. external accesses to the ram (that is, by the cpu) follow the same timing sequence as a standard slave register access, except that the target wait states required drops from 5to3. a complete set of development tools is available for writing custom drivers with scsi scripts. for more information on the scsi scripts instructions supported by the SYM53C895, see chapter 6, scsi scripts instruction set . 2.4 prefetching scripts instructions to enable the prefetch logic, set the prefetch enable bit in the dcntl register. after doing so, the prefetch logic in the SYM53C895 fetches 8 dwords of instructions. the prefetch logic automatically determines the maximum burst size that it can perform, based on the burst length as determined by the values in the dmode register. if the burst size is less than four dwords, the SYM53C895 performs normal instruction fetches. while the SYM53C895 is prefetching scripts instructions, the pci
prefetching scripts instructions 2-9 cache line size register value does not have any effect and the memory read line, memory read multiple, and memory write and invalidate commands are not used. the SYM53C895 may ?ush the contents of the prefetch buffer under certain conditions, listed below, to ensure that the chip always operates from the most current version of the software. when one of these conditions apply, the contents of the prefetch buffer are ?ushed automatically. 1. on every memory move instruction. the memory move instruction is often used to place modi?ed code directly into memory. to make sure that the chip executes all recent modi?cations, the prefetch buffer ?ushes its contents and loads the modi?ed code every time an instruction is issued. to avoid inadvertently ?ushing the prefetch buffer contents, use the no flush option for all memory move operations that do not modify code within the next 8 dwords. for more information on this instruction, refer to chapter 6. 2. on every store instruction. the store instruction may also be used to place modi?ed code directly into memory. to avoid inadvertently ?ushing the prefetch buffer contents, use the no flush option for all store operations that do not modify code within the next 8 dwords. 3. on every write to the dsp. 4. on all transfer control instructions. when the transfer conditions are met, the prefetch buffer is ?ushed. this is necessary because the next instruction to be executed is not the sequential next instruction in the prefetch buffer. 5. prefetch flush bit (dcntl bit 6) is set. the buffer ?ushes whenever this bit is set. the bit is self-clearing. 2.4.1 op code fetch burst capability setting the burst op code fetch enable bit in the dmode register (0x38) causes the SYM53C895 to burst in the ?rst two dwords of all instruction fetches. if the instruction is a memory to memory move, the third dword is accessed in a separate ownership. if the instruction is an
2-10 functional description indirect type, the additional dword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move, the SYM53C895 uses two accesses to obtain the four dwords required, in two bursts of two dwords each. note: this feature only works if prefetching is disabled. 2.5 designing an ultra2 scsi system since ultra2 scsi is based on existing scsi standards, it can use existing driver programs as long as the software is able to negotiate for ultra2 scsi synchronous transfer rates. additional software modi?cations may be needed to take advantage of the new features in the SYM53C895. in the area of hardware, lvd scsi is required to achieve ultra2 scsi transfer rates and to support the longer cable and additional devices on the bus. all devices on the bus must have lvd scsi to guarantee ultra2 scsi transfer rates. for additional information on ultra2 scsi, refer to the spi-2 working document which is available from the scsi bbs referenced at the beginning of this manual. chapter 7, electrical characteristics contains ultra2 scsi timing information. in addition to the guidelines in the draft standard, make the following software and hardware adjustments to accommodate ultra2 scsi transfers: step 1. set the ultra enable bit, bit 7 in the scntl3 register, to enable ultra2 scsi transfers. step 2. set the tolerant enable bit, bit 7 in the stest3 register, whenever the ultra enable bit is set. step 3. do not extend the sreq/sack ?ltering period with stest2 bit 1. when the ultra enable bit is set, the ?ltering period is ?xed at 8 ns for ultra2 scsi or 15 ns for ultra scsi, regardless of the value of the sreq/sack filtering bit. step 4. use the scsi clock quadrupler.
SYM53C895 interfaces 2-11 2.5.1 using the scsi clock quadrupler the SYM53C895 can quadruple the frequency of a 40 mhz scsi clock, allowing the system to perform ultra2 scsi transfers. this option is user- selectable with bit settings in the stest1, stest3, and scntl3 registers. at power-on or reset, the quadrupler is disabled and powered down. follow these steps to use the clock quadrupler: step 1. set the sclk quadrupler enable bit (stest1, bit 3). step 2. poll bit 5 of the stest4 register. the SYM53C895 sets this bit as soon as it locks in the 160 mhz frequency. the frequency lockup takes approximately 100 microseconds. step 3. halt the scsi clock by setting the halt scsi clock bit (stest3, bit 5). step 4. set the clock conversion factor using the scf (bits [6:4]) and ccf (bits [2:0]) ?elds in the scntl3 register. step 5. set the sclk quadrupler select bit (stest1, bit 2). step 6. clear the halt scsi clock bit (stest3, bit 5). 2.6 SYM53C895 interfaces this section contains information about: parallel rom interfaces serial eeprom interfaces scsi bus interfaces 2.6.1 parallel rom interface the SYM53C895 supports up to one megabyte of external memory in binary increments from 16 kbytes, to allow the use of expansion rom for add-in pci cards. the device also supports ?ash rom updates through the add-in interface and the gpio4 pin (used to control v pp , which is the power supply for programming external memory). this interface is designed for low-speed operations such as downloading instruction code from rom; it is not intended for dynamic activities such as executing instructions.
2-12 functional description system requirements include the SYM53C895, two or three external 8-bit address holding registers (hct273 or hct374), and the appropriate memory device. the 4.7 k w resistors on the memory address/data (mad) bus require use of hc or hct external components. if in-system ?ash rom updates are required, a 7406 inverter (high voltage open collector inverter), an mtd4p05, and several passive components are also needed. the memory size and speed is determined by pull-up/pull-down con?guration on the 8-bit bidirectional memory bus at power up. the SYM53C895 senses this bus shortly after the release of the reset signal and con?gures the rom base address register and the memory cycle state machines for the appropriate conditions. the SYM53C895 supports a variety of sizes and speeds of expansion rom, using pull-up and pull-down resistors on the mad[3:0]) pins. pins mad[3:1] allow the user to de?ne how much external memory is available to the SYM53C895. table 2.1 shows the memory space associated with the possible values of mad[3:1]. the mad[3:1] pins are fully de?ned in chapter 4, signal descriptions appendix b, external memory interface diagram examples shows an example set of interface drawings. to use one of the con?gurations mentioned above in a host adapter board design, put 4.7 k w pull-up and pull-down resistors on the appropriate mad pins, corresponding to the available memory space. for table 2.1 external memory support mad[3:1] available memory space 0b000 16 kbytes 0b001 32 kbytes 0b010 64 kbytes 0b011 128 kbytes 0b100 256 kbytes 0b101 512 kbytes 0b110 1024 kbytes 0b111 no external memory present
SYM53C895 interfaces 2-13 example, to connect to a 32 kbytes external rom, use pull-downs on mad(3) and mad(2) and a pull-up on mad(1). note: the sym53c875 contains internal pull-ups on the mad bus. the SYM53C895 requires external resistors to pull up the mad bus to v dd . the SYM53C895 allows the system to determine the size of the available external memory using the expansion rom base address register in the pci con?guration space. for more information on how this works, refer to the pci speci?cation or the expansion rom base address register description in chapter 5, registers . mad(0) is the slow rom pin. when pulled down, it enables two extra clock cycles of data access time, which allows use of slower memory devices. the external memory interface also supports updates to ?ash memory. the 12-volt power supply for ?ash memory, v pp , is enabled and disabled with the gpio4 pin and the gpio4 control bit. for more information on the gpio4 pin, refer to chapter 4, signal descriptions . 2.6.2 serial eeprom interface the SYM53C895 implements an interface that allows attachment of a serial eeprom device to the gpio0 and gpio1 pins. four different modes of operation are possible; each one relates to different values for the serial eeprom interface, the subsystem id register, and the subsystem vendor id register. the modes are programmable through the mad6 and mad7 pins, which are sampled at power-up or hard reset. 2.6.2.1 mode a: 4.7 k w pull-ups on mad6 and mad7 in this mode, gpio0 is the serial data signal (sda) and gpio1 is the serial clock signal (scl). certain data in the serial eeprom is automatically loaded into chip registers at power-up or hard reset. the format of the serial eeprom data is de?ned in table 2.2 . if the eeprom is not present, or the checksum fails, the subsystem id and subsystem vendor id registers read back all zeroes. at power-up or hard reset, only ?ve bytes are loaded into the chip from locations 0x00 through 0x04.
2-14 functional description 2.6.2.2 mode b: 4.7 k w pull-down on mad6, and 4.7 k w pull-up on mad7 in this mode, gpio0 and gpio1 are each de?ned as either the serial data signal (sda) or the serial clock signal (scl), since both pins are controlled through software. no data is automatically loaded into chip registers at power-up or hard reset. the subsystem id register and subsystem vendor id registers are read/write, in violation of the pci speci?cation, with a default value of all zeroes. 2.6.2.3 mode c: 4.7 k w pull-downs on mad6 and mad7 in this mode, gpio1 is the serial data signal (sda) and gpio0 is the serial clock signal (scl). certain data in the serial eeprom is automatically loaded into chip registers at power-up or hard reset. table 2.2 mode a serial eeprom data format byte description 0x00 subsystem vendor id, lsb. this byte is loaded into the least signi?cant byte of the subsystem vendor id register in pci con?guration space at chip power-up or hard reset. 0x01 subsystem vendor id, msb. this byte is loaded into the most signi?cant byte of the subsystem vendor id register in pci con?guration space at chip power-up or hard reset. 0x02 subsystem id, lsb. this byte is loaded into the least signi?cant byte of the subsystem id register in pci con?guration space at chip power-up or hard reset. 0x03 subsystem id, msb. this byte is loaded into the most signi?cant byte of the subsystem id register in pci con?guration space at chip power-up or hard reset. 0x04 checksum. this 8-bit checksum is formed by adding, bytewise, each byte contained in locations 0x00C0x03 to the seed value 0x55, and then taking the 2s compliment of the result. 0x05C0xff reserved. 0x100Ceom contains user data.
SYM53C895 interfaces 2-15 the format of the serial eeprom data is de?ned in table 2.3 . if the eeprom is not present, or the checksum fails, the subsystem id and subsystem vendor id registers read back all zeroes. at power-up or hard reset, only ?ve bytes are loaded into the chip from locations 0xfb through 0xff. 2.6.2.4 mode d: 4.7 k w pull-up on mad6, and 4.7 k w pull-down on mad7 this is a reserved mode and should not be used. 2.6.3 scsi bus interface the SYM53C895 performs se and lvd transfers, and supports traditional (high-power) differential operation when the chip is connected to external high-power differential transceivers. to support lvd scsi, all scsi data and control signals have a positive and a negative signal line, as in high voltage differential. in se and hvd operation, the negative signals perform the scsi data and control table 2.3 mode c serial eeprom data format byte description 0x00C0xfa contains user data. 0xfb subsystem vendor id, lsb. this byte is loaded into the least signi?cant byte of the subsystem vendor id register in pci con?guration space at chip power-up or hard reset. 0xfc subsystem vendor id, msb. this byte is loaded into the most signi?cant byte of the subsystem vendor id register in pci con?guration space at chip power-up or hard reset. 0xfd subsystem id, lsb. this byte is loaded into the least signi?cant byte of the subsystem id register in pci con?guration space at chip power-up or hard reset. 0xfe subsystem id, msb. this byte is loaded into the most signi?cant byte of the subsystem id register in pci con?guration space at chip power-up or hard reset. 0xff checksum. this 8-bit checksum is formed by adding, bytewise, each byte contained in locations 0xfbC0xfe to the seed value 0x55, and then taking the 2s compliment of the result. 0x100Ceom contains user data.
2-16 functional description function. in hvd mode, the positive signals provide directional control and in se mode they are virtual ground drivers. tolerant technology provides signal ?ltering at the inputs of sreq/ and sack/ to increase immunity to signal re?ections. 2.6.3.1 lvd link technology to support greater device connectivity and a longer scsi cable, the SYM53C895 features lvd link technology, which is the lsi logic implementation of lvd scsi. lvd link transceivers provide the inherent reliability of differential scsi and a long-term migration path of faster scsi transfer rates. lvd link technology is based on current drive; its low output current reduces the power needed to drive the scsi bus, so that the i/o drivers can be integrated directly onto the chip. this reduces the cost and complexity compared to traditional (high power) differential designs. lvd link lowers the amplitude of noise re?ections and allows higher transmission frequencies. the symbios lvd link transceivers operate in lvd and se modes. they allow the chip to detect a high voltage differential signal when the chip is connected to external high voltage differential transceivers. the SYM53C895 automatically detects which type of signal is connected, based on voltage detected by the diffsens pin. bits 7 and 6 of the stest4 register contain the encoded value for the type of signal that is detected (lvd, se, or high voltage differential). refer to the stest4 register description for encoding and other bit information. 2.6.3.2 high voltage differential mode (hvd) to maintain backward compatibility with legacy systems, the SYM53C895 can operate in hvd mode (when the chip is connected to external differential transceivers). in high voltage differential mode, the sd+ [15:0], sdp+ [1:0], req+, ack+, rst+, bsy+, and sel+ signals control the direction of external differential-pair transceivers. the SYM53C895 is placed in differential mode by setting the dif bit, bit 5 of the stest2 register (0x4e). setting this bit 3-states the bsy - , sel - , and rst - pads so they can be used as pure input pins. in addition to the standard scsi lines, the SYM53C895 uses these signals during high voltage differential operation as shown in table 2.4:
SYM53C895 interfaces 2-17 in the differential wiring diagram example shown in figure 2.7 , the SYM53C895 is connected to the ti sn75976a2 differential transceiver for ultra scsi operation. the recommended value of the pull-up resistor on the req - ,ack - , msg - , c/d - , i/o - ,atn - , sd[7:0] - , and sdp0 - lines is 680 w when the active negation portion of symbios tolerant technology is not enabled. when tolerant is enabled, the recommended resistor value on the req - ,ack - , sd[7:0] - , and sdp0 - signals is 1.5 k w . the electrical characteristics of these pins change when tolerant is enabled, permitting a higher resistor value. to interface the SYM53C895 to the sn75976a2, connect the positive pins in the scsi lvd pair of the SYM53C895 directly to the transceiver enables (nde/re/). these signals control the direction of the channels on the sn75976a2. the scsi bidirectional control and data pins (sd[7:0] - sdp0 - , req - , ack - , msg - , i_o - , c_d - , and atn - ) of the SYM53C895 connect to the bidirectional data pins (na) of the sn75976a2 with a pull-up resistor. the pull-up value should be no lower than the transceiver i ol can tolerate, but not so high as to cause rc timing problems. the three remaining pins, sel - , bsy - , and rst - , are connected to the sn75976a2 with a table 2.4 high voltage differential operation signal function bsy+, sel+, rst+ active high signals used to enable the differential drivers as outputs for scsi signals bsy - , sel - , and rst - , respectively sd+[15:0], sdp+[1:0] active high signals used to control direction of the differential drivers for scsi data and parity lines, respectively ack+ active high signal used to control direction of the differential driver for initiator group signals atn - and ack - req+ active high signal used to control direction of the differential drivers for target group signals msg - , c/d - , i/o - and req /- diffsens input to the SYM53C895 used to detect the voltage level of a scsi signal to determine whether it is a se, lvd, or hvd signal. the result is displayed in stest4 bits [7:6].
2-18 functional description pull-down resistor. the pull-down resistors are required when the pins (na) of the sn75976a2 are con?gured as inputs. when the data pins are inputs, the resistors provide a bias voltage to both the SYM53C895 pins (sel - , bsy - , and rst - ) and the sn75976a2 data pins. because the sel - , bsy - , and rst - pins on the SYM53C895 are inputs only, this con?guration allows for the sel - , bsy - , and rst - scsi signals to be asserted on the scsi bus. the differential pairs on the scsi bus are reversed when connected to the sn75976a2, due to the active low nature of the scsi bus. 8-bit/16-bit scsi and the high voltage differential interface C in an 8-bit scsi bus, the sd[15:8] pins on the SYM53C895 should be pulled up with a 1.5 k w resistor or terminated like the rest of the scsi bus lines. this is very important, as errors may occur during reselection if these lines are left ?oating.
SYM53C895 interfaces 2-19 figure 2.3 8-bit high voltage differential wiring diagram for ultra2 scsi sym53c8xx ssel+ sbsy+ srst+ ssel - sbsy - srst - sreq - sack - smsg - scd - s io - satn - sreq+ sack+ sd[8:15]+ sdp1+ sd[8:15] - sdp1 - sdp0+ sd7+ sd6+ sd5+ sd4+ sd3+ sd1+ sd0+ sd2+ sdp0 - sd7 - sd6 - sd5 - sd4 - sd3 - sd1 - sd0 - sd2 - diffsens sn75976a2 diffsens schottky diode diffsens (pin 21) cde0 cde1 cde2 bsr cre/ 1a 1de/re/ 2a 2de/re/ 3a 3de/re/ 4a 4de/re/ 6a 6de/re/ 7a 7de/re/ 8a 8de/re/ 9a 9de/re/ 5a 5de/re/ vdd ssel+ sbsy+ srst+ ssel - sbsy - srst - 1.5 k w vdd 1.5 k w vdd 1.5 k w req/ sack - smsg - scd - sio - satn - vdd 1.5 k w sn75976a diffsens cde0 cde1 cde2 bsr cre/ 1a 1de/re/ 2a 2de/re/ 3a 3de/re/ 4a 4de/re/ 6a 6de/re/ 7a 7de/re/ 8a 8de/re/ 9a 9de/re 5a 5de/re/ sd0+ sd1+ sd2+ sd0 - sd1 - sd2 - sd3 - sd4 - sd5 - sd6 - sd7 - sdp0 - sd3+ sd4+ sd5+ sd6+ sd7+ sdp0+ float float vdd 1.5 k w vdd 1.5 k w diffsens 1b+ 1b - 2b+ 2b - 3b+ 3b - 4b+ 4b - 5b+ 5b - 6b+ 6b - 7b+ 7b - 8b+ 8b - 9b+ 9b - 1b+ 1b - 2b+ 2b - 3b+ 3b - 4b+ 4b - 5b+ 5b - 6b+ 6b - 7b+ 7b - 8b+ 8b - 9b+ 9b - - ssel (42) +ssel (41) - sbsy (34) +sbsy (33) - srst (38) +srst (37) - sreq (46) +sreq (45) - sack (36) +sack (35) - sc_d (44) +sc_d (43) - si_o (48) +si_o (47) - satn (30) +satn (29) - smsg (40) +smsg (39) scsi bus - sd0 (4) +sd0 (3) - sd1 (6) +sd1 (5) - sd2 (8) +sd2 (7) - sd3 (10) +sd3 (9) - sd4 (12) +sd4 (11) - sd5 (14) +sd5 (13) - sd6 (16) +sd6 (15) - sd7 (18) +sd7 (17) - sdp (20) +sdp (19) 1.5 k w
2-20 functional description 2.7 SYM53C895 modes this section provides information about: pci cache mode big and little endian modes loopback mode 2.7.1 pci cache mode the SYM53C895 supports the pci speci?cation for an 8-bit cache line size register located in pci con?guration space. the cache line size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. in conjunction with the cache line size register, the pci commands read line, read multiple, and write and invalidate are each software enabled or disabled to allow the user full ?exibility in using these commands. for more information on pci cache mode operations, refer to chapter 3, pci functional description. 2.7.2 big and little endian modes the SYM53C895 supports both big and little endian byte ordering through pin selection. in big endian mode, the ?rst byte of an aligned scsi to pci transfer is routed to lane three and successive transfers are routed to descending lanes. this mode of operation also applies to data transfers over the add-in rom interface. the byte of data accessed at memory location 0x0000 is routed to lane three, and the data at location 0x0003 is routed to byte lane 0. in little endian mode, the ?rst byte of an aligned scsi to pci transfer is routed to lane zero and successive transfers are routed to ascending lanes. this mode of operation also applies to the add-in rom interface. the byte of data accessed at memory location 0x0000 is routed to lane zero, and the data at memory location 0x0003 is routed to byte lane 3. the big_lit pin gives the SYM53C895 the ?exibility of operating with either big or little endian byte orientation. internally, in either mode, the actual byte lanes of the dma fifo and registers are not modi?ed. the SYM53C895 supports slave accesses in big or little endian mode.
SYM53C895 modes 2-21 when a dword is accessed, no repositioning of the individual bytes is necessary since dwords are addressed by the address of the least signi?cant byte. scripts always uses dwords in 32-bit systems, so compatibility is maintained between systems using different byte orientations. when less than a dword is accessed, individual bytes must be repositioned. internally, the SYM53C895 adjusts the byte control logic of the dma fifo and register decodes to access the appropriate byte lanes. the registers always appear on the same byte lane, but the address of the register is repositioned. big and little endian mode selection has the most effect on individual byte access. internally, the SYM53C895 adjusts the byte control logic of the dma fifo and register decodes to enable the appropriate byte lane. the registers always appear on the same byte lane, but the address of the register is repositioned. data to be transferred between system memory and the scsi bus always starts at address zero and continues through address n. no byte ordering exists in the chip. the ?rst byte in from the scsi bus goes to address 0, the second to address 1, etc. going out onto the scsi bus, address zero is the ?rst byte out on the scsi bus, address 1 is the second byte, etc. the only difference is that in a little endian system, address 0 is on byte lane 0, and in big endian mode address 0 is on byte lane 3. correct scripts are generated if the scripts compiler is run on a system that has the same byte ordering as the target system. any scripts patching in memory must patch the instruction with the byte ordering that the scripts processor expects. software drivers for the SYM53C895 should access registers by their logical name (that is, scntl0) rather than by their address. the logical name should be equated to the register big endian address in big endian mode (scntl0 = 0x03), and its little endian address in little endian mode (scntl0 = 0x00). in this way, no change occurs to the software when moving from one mode to the other; only the equate statement setting the operating modes needs to be changed. addressing of registers from within a scripts instruction is independent of bus mode. internally, the SYM53C895 always operates in little endian mode.
2-22 functional description 2.7.3 loopback mode the SYM53C895 loopback mode allows testing of both initiator and target functions and, in effect, lets the chip communicate with itself. when the loopback enable bit is set in the stest1 register, the SYM53C895 allows control of all scsi signals, whether the SYM53C895 is operating in initiator or target mode. for more information on this mode of operation, refer to the symbios sym53c8xx pci-scsi i/o processors programming guide . 2.8 parity options the SYM53C895 implements a ?exible parity scheme that allows control of the parity sense, allows parity checking to be turned on or off, and has the ability to deliberately send a byte with bad parity over the scsi bus to test parity error recovery procedures. table 2.5 de?nes the bits that are involved in parity control and observation. table 2.6 describes the parity control function of the enable parity checking and assert scsi even parity bits in the scsi control zero (scntl0) register. table 2.7 describes the options available when a parity error occurs. table 2.5 bits used for parity control and generation bit name location description assert satn/ on parity errors scsi control zero (scntl0), bit 1 causes the SYM53C895 to automatically assert satn/ when it detects a parity error while operating as an initiator. enable parity checking scsi control zero (scntl0), bit 3 enables the SYM53C895 to check for parity errors. the SYM53C895 checks for odd parity. assert even scsi parity scsi control one (scntl1), bit 2 determines the scsi parity sense generated by the SYM53C895 to the scsi bus. disable halt on satn/ or a parity error (target mode only) scsi control one (scntl1), bit 5 causes the SYM53C895 not to halt operations when a parity error is detected in target mode. enable parity error interrupt scsi interrupt enable zero (sien0), bit 0 determines whether the SYM53C895 generates an interrupt when it detects a scsi parity error. parity error scsi interrupt status zero (sist0), bit 0 this status bit is set whenever the SYM53C895 has detected a parity error on the scsi bus.
parity options 2-23 status of scsi parity signal scsi status zero (sstat0), bit 0 this status bit represents the active high current state of the scsi sdp0 parity signal. scsi sdp1 signal scsi status two (sstat2), bit 0 this bit represents the active high current state of the scsi sdp1 parity signal. latched scsi parity scsi status two (sstat 2), bit 3 scsi status one (sstat1), bit 3 these bits re?ect the scsi odd parity signal corresponding to the data latched into the scsi input data latch (sidl) register master parity error enable chip test four (ctest4), bit 3 enables parity checking during master data phases. master data parity error dma status (dstat), bit 6 set when the SYM53C895 as a master detects that a target device has signalled a parity error during a data phase. master data parity error interrupt enable dma interrupt enable (dien), bit 6 by clearing this bit, a master data parity error does not cause irq/ to be asserted, but the status bit is set in the dma status (dstat) register. enable parity error response command, bit 6 parity checking and parity error reporting are enabled on the pci bus. table 2.6 scsi parity control epc 1 1. key: epc = enable parity checking (bit 3 scsi control zero (scntl0)) asep = assert scsi even parity (bit 2 scsi control one (scntl1)) aesp 1 description 0 0 does not check for parity errors. parity is generated when sending scsi data. asserts odd parity when sending scsi data. 0 1 does not check for parity errors. parity is generated when sending scsi data. asserts even parity when sending scsi data. 1 2 2. this table only applies when the enable parity checking bit is set.(scntl0) 0 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts odd parity when sending scsi data. 1 1 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts even parity when sending scsi data. table 2.5 bits used for parity control and generation (cont.) bit name location description
2-24 functional description 2.8.1 scsi termination the terminator networks provide the biasing needed to pull signals to an inactive voltage level. they also match the impedance seen at the end of the cable with the characteristic impedance of the cable. terminators must be installed at the extreme ends of the scsi chain, and only at the ends. no system should ever have more or less than two terminators installed and active. scsi host adapters should provide a means of accommodating terminators. the terminators should be socketed, so that if not needed they can be removed, or there should be a means of disabling them with software. single-ended cables can use a 220 w pull-up to the terminator power supply (term-power) line and a 330 w pull-down to ground. due to the high-performance nature of the SYM53C895, regulated (or active) termination is recommended. figure 2.4 shows a unitrode active terminator. for additional information, refer to the scsi-2 speci?cation. tolerant active negation can be used with either termination network. for information on terminators that support lvd, refer to the spi-2 draft standard. note: when using the SYM53C895 in a design with an 8-bit scsi bus, all 16 data lines still must be terminated or pulled high. table 2.7 scsi parity errors and interrupts dhp 1 1. key: dhp = disable halt on satn/ or parity error (bit 5 scsi control one (scntl1)) par = parity error (bit 0 scsi interrupt enable zero (sien0)) par description 0 0 halts when a parity error occurs in target or initiator mode and does not generate an interrupt. 0 1 halts when a parity error occurs in target mode and generates an interrupt in target or initiator mode. 1 0 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt is not generated. 1 1 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt is generated.
parity options 2-25 figure 2.4 regulated termination for ultra2 scsi 2.8.2 system engineering note in the SYM53C895, transmission mode detection for single-ended (se), high voltage differential (hvd), and low voltage differential (lvd) is implemented by using the diffsens line. table 2.8 shows the corresponding voltages and what mode they indicate. the scsi parallel interface 2 speci?cation revision 1.1 (spi-2) has timing speci?c mode requirements that state a bus mode change must be sensed for at least a continuous 100 ms to be valid. the signal drivers should remain in a high impedance state at power-up until the device is capable of full logical operation for at least 100 ms. the bus mode 4 line1+ 5 line1 - 6 line2+ 7 line2 - 11 line3+ 12 line3 - 13 line4+ 14 line4 - 15 line5+ 16 line5 - 17 discnct line9 - 32 line9+ 31 line8 - 30 line8+ 29 line7 - 25 line7+ 24 line6 - 23 line6+ 22 diff sense 20 sd0+ sd0 - sd1+ sd1 - sd2+ sd2 - sd3+ sd3 - sd4+ sd4 - sdp0+ sdp0 - sd7+ sd7 - sd6+ sd6 - sd5+ sd5 - diff sense connects to the scsi bus diffsense line to detect what type of devices (single-ended, lvd, or hvd) are connected to the scsi bus. dscnct shuts down the terminator when it is not at the end of the bus. the disconnect pin low enables the terminator. use additional ucc6350 terminators to connect signals and additional wide scsi data bytes as needed. table 2.8 transmission mode mode se lvd hvd voltage - 0.35 to + 0.5 0.7 to 1.9 2.4 to 5.5
2-26 functional description detected by the diffsens line has remained stable for at least another 100 ms after that. in order to achieve the suf?cient 100 ms delay required by the standard, follow these steps when a mode change is detected. at power-up: step 1. set bit 3 in stest2 (register 0x4e), to place the scsi drivers in a high impedance state. step 2. enable the scsi bus mode change (sbmc) interrupt by setting bit 4 in scsi interrupt enable one (sien1) (register 0x41). step 3. if a scsi bus mode change is detected, then scsi interrupt status one (sist1-register 0x43), bit 4 indicates a sbmc interrupt. step 4. clear the interrupt by reading scsi interrupt status zero (sist0-register 0x42) and sist1. step 5. wait 100 ms. step 6. check that no more sbmc interrupts have occurred. if not, the diffsens line has not changed voltage levels and the bus mode is stable so then proceed to: a. read bits [7:6] in stest4 (register 0x52). b. write these two bits to stest0 (register 0x4c), bits [5:4]. this forces the scsi bus mode to the correct operating mode. note: if an sbmc interrupt occurs between steps 4 and 6, handle the interrupt and return to step 3. bits [5:4] in stest0 are normally used as part of the ssaid and are read only. these bits may be written as part of a special test mode that forces the scsi bus mode to one of three operating modes: se, lvd, or hvd. the bit encoding is the same that is shown in the table 5.11 under stest4 for bits [7:6]. step 7. clear bit 3 in stest2 to remove the sci drivers from the high impedance state.
parity options 2-27 during normal operation: step 1. enable the scsi bus mode change (sbmc) interrupt. bit 4 in sien1 should be set. step 2. if a scsi bus mode change is detected, scsi interrupt status one (sist1) bit 4 indicates a scsi bus mode change (sbmc) interrupt. step 3. clear the interrupt by reading scsi interrupt status zero (sist0) and sist1. step 4. wait 100 ms. step 5. check that no more sbmc interrupts have occurred. if not, the diffsens line has not changed voltage levels and the bus mode is stable so then proceed to: a. read bits [7:6] in scsi test four (stest4). b. write two bits 5 and 4 to scsi test zero (stest0). note: bits [5:4] in stest0 are normally used as part of the ssaid and are read only. these bits may be written as part of a special test mode that forces the scsi bus mode to one of three operating modes: se, lvd, or hvd. the bit encoding is the same that is shown in the table 5.11 under stest4 for bits [7:6]. this forces the scsi bus to the correct operating mode. if a sbmc interrupt did occur between steps 3 and 5, handle the interrupt and return to step 3. the sbmc interrupt can cause a problem in systems that use multiple software drivers where the drivers pass control to one another after a chip reset. this problem occurs when the SYM53C895 is connected to a single-ended scsi bus because the sbmc interrupt is generated after each reset. in particular, this problem occurs with netware when control is passed between the netware and dos drivers. after a soft reset, the SYM53C895 defaults to lvd mode. if single-ended devices are on the bus and pull the diffsens line low, a sbmc interrupt is generated and requires a response from the driver.
2-28 functional description one solution is to use a soft abort by writing a one to bit 7 in the interrupt status (istat) register instead of a soft reset to stop current scsi transactions. this would halt current transactions without altering chip settings such as the clock quadrupler and the clock divider setup. the pending transactions would then start over. 2.8.3 (re)select during (re)selection in multithreaded scsi i/o environments, it is not uncommon to be selected or reselected while trying to perform selection/reselection. this situation may occur when a scsi controller (operating in initiator mode) tries to select a target and is reselected by another. the select scripts instruction has an alternate address to which the scripts jump when this situation occurs. an analogous situation occurs for target devices being selected while trying to perform a reselection. once a change in operating mode occurs, the initiator scripts should start with a set initiator instruction or the target scripts should start with a set target instruction. the selection and reselection enable bits (scid bits 5 and 6, respectively) should both be asserted so that the SYM53C895 may respond as an initiator or as a target. if only selection is enabled, the SYM53C895 cannot be reselected as an initiator. there are also status and interrupt bits in the scsi interrupt status one (sist0) and scsi interrupt enable zero (sien0) registers that indicate whether the SYM53C895 has been selected (bit 5) and reselected (bit 4). 2.9 synchronous operation the SYM53C895 can transfer synchronous scsi data in both initiator and target modes. the scsi transfer (sxfer) register controls both the synchronous offset and the transfer period. it can be loaded by the cpu before scripts execution begins, from within scripts by using a table indirect i/o instruction, or with a read-modify-write instruction. the SYM53C895 can receive data from the scsi bus at a synchronous transfer period as short as 25 ns, regardless of the transfer period used to send data. the SYM53C895 can receive data at one-fourth of the divided sclk frequency. depending on the sclk frequency, the negotiated transfer period, and the synchronous clock divider, the SYM53C895 can send synchronous data at intervals as short as 25 ns for ultra2 scsi, 50 ns for ultra scsi, 100 ns for fast scsi and 200 ns for scsi-1.
synchronous operation 2-29 2.9.1 determining the data transfer rate synchronous data transfer rates are controlled by bits in two different registers of the SYM53C895. a brief description of the bits is provided below. figure 2.5 illustrates the clock division factors used in each register, and the role of the register bits in determining the transfer rate. 2.9.1.1 scsi control three (scntl3) register, bits [6:4] (scf[2:0]) the scf[2:0] bits select the factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. the output from this divider controls the rate at which data can be received. this rate must not exceed 160 mhz. the receive rate of synchronous scsi data is 1/4 of the scf divider output. for example, if sclk is 160 mhz and the scf value is set to divide by one, then the maximum rate at which data can be received is 40 mhz (160/(1*4) = 40). 2.9.1.2 scsi control three (scntl3) register, bits [2:0] (ccf[2:0]) the ccf[2:0] bits select the factor by which the frequency of sclk is divided before being presented to the asynchronous scsi core logic. this divider must be set according to the input clock frequency in the figure 2.5 . 2.9.1.3 scsi transfer (sxfer) register, bits [7:5] (tp[2:0]) the tp[2:0] divider bits determine the scsi synchronous transfer period when sending synchronous scsi data in either initiator or target mode. this value further divides the output from the scf divider. 2.9.2 ultra2 scsi synchronous data transfers ultra2 scsi is an extension of current ultra scsi synchronous transfer speci?cations. it allows negotiation of synchronous transfer periods as short as 25 ns, which is half the 50 ns period allowed under ultra scsi. this allows a maximum transfer rate of 80 mbytes/s on a 16-bit, lvd scsi bus. the SYM53C895 has a scsi clock quadrupler that must be enabled for the chip to perform ultra2 scsi transfers with a 40 mhz oscillator. in addition, the following bit values affect the chips ability to support ultra2 scsi synchronous transfer rates:
2-30 functional description clock conversion factor bits, scsi control three (scntl3) register bits [2:0] and synchronous clock conversion factor bits, scntl3 register bits [6:4]. these ?elds support a value of 0b111, which allows the 160 mhz sclk frequency to be divided down by 8 for the asynchronous logic. ultra2 scsi enable bit, scntl3 register bit 7. setting this bit enables ultra2 scsi synchronous transfers in systems that use the internal scsi clock quadrupler. tolerant enable bit, scsi test three (stest3) register bit 7. active negation must be enabled for the SYM53C895 to perform ultra2 scsi transfers. note: the clock quadrupler requires a 40 mhz external clock. symbios software assumes that the SYM53C895 is connected to a 40 mhz external clock, which is quadrupled to achieve ultra2 scsi transfer rates.
synchronous operation 2-31 figure 2.5 determining the synchronous transfer rate ccf2 ccf1 ccf0 qclk (mhz) 0 0 0 50.1C66.00 0 0 1 16.67C25.00 0 1 0 25.01C37.50 0 1 1 37.51C50.00 1 0 0 50.01C66.00 1 0 1 75.01C80.00 110120 111160 example: qclk (quadrupled scsi clock) = 160 mhz, scf = 1(/1), xferp = 0(/4), ccf = 7 (/8) synchronous send rate = (qclk/scf)/xferp = (160/1)/4 = 40 mbytes/s synchronous receive rate = (qclk/scf)/4 = (160/1)/4 = 40 mbytes/s divide by 4 tp2 tp1 tp0 xferp divisor 000 4 001 5 010 6 011 7 100 8 101 9 110 10 111 11 sclk scf ccf asynchronous send clock divider divider scsi logic scf2 scf1 scf0 scf divisor 0 011 0 1 0 1.5 0 112 1 003 0 003 1 014 1 106 1 118 this point must not exceed 160 mhz receive clock (to scsi bus) synchronous divider clock quadrupler qclk
2-32 functional description 2.10 interrupt handling the scripts processor in the SYM53C895 performs most functions independently of the host microprocessor. however, certain interrupt situations must be handled by the external microprocessor. this section explains all aspects of interrupts as they apply to the SYM53C895. 2.10.1 polling and hardware interrupts the external microprocessor is informed of an interrupt condition by polling or hardware interrupts. polling means that the microprocessor must continually loop and read a register until it detects a bit set that indicates an interrupt. this method is the fastest, but it wastes cpu time that could be used for other system tasks. the preferred method of detecting interrupts in most systems is hardware interrupts. in this case, the SYM53C895 asserts the interrupt request (irq/) line that interrupts the microprocessor, causing the microprocessor to execute an interrupt service routine. a hybrid approach would use hardware interrupts for long waits, and use polling for short waits. 2.10.2 registers the registers in the SYM53C895 that are used for detecting or de?ning interrupts are: interrupt status (istat) scsi interrupt status zero (sist0) scsi interrupt status one (sist1) dma status (dstat) scsi interrupt enable zero (sien0) scsi interrupt enable one (sien1) dma control (dcntl) dma interrupt enable (dien)
interrupt handling 2-33 2.10.2.1 istat istat is the only register that can be accessed as a slave during scripts operation; therefore, the istat register is polled when polled interrupts are used. it is also the ?rst register that should be read when the irq/ pin has been asserted in association with a hardware interrupt. the interrupt on the fly (intf) bit should be the ?rst interrupt serviced. it must be written to one to be cleared. this interrupt must be cleared before servicing any other interrupts. if the sip bit in the istat register is set, then a scsi-type interrupt has occurred and the sist0 and sist1 registers should be read. if the dip bit in the istat register is set, then a dma-type interrupt has occurred and the dstat register should be read. scsi-type and dma-type interrupts may occur simultaneously, so in some cases both sip and dip may be set. 2.10.2.2 sist0 and sist1 sist0 and sist1 registers contain the scsi-type interrupt bits. reading these registers determines which condition or conditions caused the scsi-type interrupt, and clears that scsi interrupt condition. if the SYM53C895 is receiving data from the scsi bus and a fatal interrupt condition occurs, the SYM53C895 attempts to send the contents of the dma fifo to memory before generating the interrupt. if the SYM53C895 is sending data to the scsi bus and a fatal scsi interrupt condition occurs, data could be left in the dma fifo. if this situation occurs, the dma fifo empty (dfe) bit in dma status (dstat) should be checked. if this bit is cleared, set the clear dma fifo (clf) and clear scsi fifo (csf) bits before continuing. the clf bit is bit 2 in ctest3. the csf bit is bit 1 in stest3. 2.10.2.3 dstat the dstat register contains the dma-type interrupt bits. reading this register determines which condition or conditions caused the dma-type interrupt, and clears that dma interrupt condition. bit 7, dfe bit in dstat is purely a status bit; it does not generate an interrupt under any circumstances and is not cleared when read. dma interrupts ?ushes
2-34 functional description neither the dma nor scsi fifos before generating the interrupt, so the dfe bit in the dstat register should be checked after any dma interrupt. if the dfe bit is cleared, then the fifos must be cleared by setting the clear dma fifo (clf) and clear scsi fifo (csf) bits. setting the flush dma fifo (flf) bit ?ushes the fifo. 2.10.2.4 sien0 and sien1 the sien0 and sien1 registers are the interrupt enable registers for the scsi interrupts in scsi interrupt status zero (sist0) and scsi interrupt status one (sist1). 2.10.2.5 dien the dien register is the interrupt enable register for dma interrupts in dma status (dstat). 2.10.2.6 dcntl when bit 1 in the dcntl register is set, the irq/ pin is not asserted when an interrupt condition occurs. the interrupt is not lost or ignored, but merely masked at the pin. clearing this bit when an interrupt is pending immediately asserts the irq/ pin. as with any register other than i s tat, this register can only be accessed by a scripts instruction during scripts execution. 2.10.3 fatal vs. nonfatal interrupts a fatal interrupt, as the name implies, always stops scripts from running. all nonfatal interrupts become fatal when they are enabled by setting the appropriate interrupt enable bit. interrupt masking is discussed later in section 2.10.4, masking, page 2-35 . all dma interrupts (indicated by the dip bit in istat and one or more bits in dstat being set) are fatal. some scsi interrupts are nonfatal. these are indicated by the sip bit in the istat and one or more bits in sist0 or sist1 being set. when the SYM53C895 is operating in initiator mode, only the function complete (cmp), selected (sel), reselected (rsl), general purpose timer expired (gen), and handshake to handshake timer expired (hth)
interrupt handling 2-35 interrupts are nonfatal. when operating in target mode cmp, sel, rsl, target mode: satn/ active (m/a), gen, and hth are nonfatal. refer to the description for the disable halt on a parity error or satn/ active (target mode only) (dhp) bit in the scsi control one (scntl1) register. this information describes how to con?gure the chip behavior when the satn/ interrupt is enabled during target mode operation. the interrupt on the fly interrupt is also nonfatal, since scripts can continue when it occurs. nonfatal interrupts prevent scripts from stopping when an interrupt occurs that does not require service from the cpu. scripts do not stop when: arbitration is complete (cmp set). the SYM53C895 has been selected or reselected (sel or rsl set). the initiator has asserted atn (target mode: satn/ active). the general purpose or handshake-to-handshake timers expire. these interrupts are not needed for events that occur during high-level scripts operations. 2.10.4 masking masking an interrupt means disabling or ignoring that interrupt. interrupts can be masked by clearing bits in the sien0 and sien1 (for scsi interrupts) registers or dien (for dma interrupts) register. how the chip responds to masked interrupts depends on whether: polling or hardware interrupts are being used. the interrupt is fatal or nonfatal. the chip is operating in initiator or target mode. if a nonfatal interrupt is masked and that condition occurs, scripts do not stop, the appropriate bit in the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) is still set, the sip bit in the istat is not set, and the irq/ pin is not asserted. see subsection entitled fatal vs. nonfatal interrupts for a list of the nonfatal interrupts.
2-36 functional description if a fatal interrupt is masked and that condition occurs, then scripts still stop, the appropriate bit in the ds tat, sist0, or sist1 register is set, and the sip or dip bits in the istat is set, but the irq/ pin is not asserted. when the chip is initialized, enable all fatal interrupts if you are using hardware interrupts. if a fatal interrupt is disabled and that interrupt condition occurs, the scripts halt and the system does not detect it unless it times out and checks the interrupt status (istat) after a certain period of inactivity. if istat is being polled instead of using hardware interrupts, then masking a fatal interrupt makes no difference since the sip and dip bits in the istat inform the system of interrupts, not the irq/ pin. masking an interrupt after irq/ is asserted does not deassert irq/. 2.10.5 stacked interrupts the SYM53C895 stacks interrupts if they occur one after the other. if the sip or dip bits in the interrupt status (istat) register are set (?rst level), then at least one pending interrupt already exists, and any future interrupts are stacked in extra registers behind the scsi interrupt status zero (sist0), scsi interrupt status one (sist1), and dma status (dstat) registers (second level). when two interrupts have occurred and the two levels of the stack are full, any further interrupts set additional bits in the extra registers behind sist0, sist1, and dma status (dstat). when the ?rst level of interrupts are cleared, all the interrupts that came in afterward move into the sist0, sist1, and ds tat. after the ?rst interrupt is cleared by reading the appropriate register, these three events occur: 1. the irq/ pin is deasserted for a minimum of three clks. 2. the stacked interrupt(s) move into the sist0, sist1, or ds tat. 3. the irq/ pin is asserted once again. since a masked nonfatal interrupt does not set the sip or dip bits, interrupt stacking does not occur. a masked, nonfatal interrupt still posts the interrupt in sist0, but does not assert the irq/ pin. since no interrupt is generated, future interrupts move right into the sist0 or
interrupt handling 2-37 sist1 instead of being stacked behind another interrupt. when another condition occurs that generates an interrupt, the bit corresponding to the earlier masked nonfatal interrupt is still set. a related situation to interrupt stacking is when two interrupts occur simultaneously. since stacking does not occur until the sip or dip bits are set, there is a small timing window in which multiple interrupts can occur but is not stacked. these could be multiple scsi interrupts (sip set), multiple dma interrupts (dip set), or multiple scsi and multiple dma interrupts (both sip and dip set). as previously mentioned, dma interrupts do not attempt to ?ush the fifos before generating the interrupt. it is important to set either the clear dma fifo (clf) and clear scsi fifo (csf) bits if a dma interrupt occurs and the dma fifo empty (dfe) bit is not set. this is because any future scsi interrupts are not posted until the dma fifo is clear of data. these locked out scsi interrupts are posted as soon as the dma fifo is empty. 2.10.6 halting in an orderly fashion when an interrupt occurs, the SYM53C895 attempts to halt in an orderly fashion as explained below. if the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a bus fault. execution does not begin, but the dsp points to the next instruction since it is updated when the current instruction is fetched. if the dma direction is a write to memory and a scsi interrupt occurs, the SYM53C895 attempts to ?ush the dma fifo to memory before halting. under any other circumstances, only the current cycle is completed before halting, so the dfe bit in dstat should be checked to see if any data remains in the dma fifo. scsi sreq/sack handshakes that have begun are completed before halting. the SYM53C895 attempts to clean up any outstanding synchronous offset before halting. in the case of transfer control instructions and once instruction execution begins, it continues to completion before halting.
2-38 functional description if the instruction is a jump/call when/if , the dma scripts pointer (dsp) is updated to the transfer address before halting. all other instructions may halt before completion. 2.10.7 sample interrupt service routine a sample of an interrupt service routine for the SYM53C895 is shown below. this routine can be repeated if polling is used, or should be called when the irq/ pin is asserted if using hardware interrupts. 1. read is tat. 2. if the intf bit is set, it must be written to a one to clear this status. 3. if only the sip bit is set, read scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) to clear the scsi interrupt condition and get the scsi interrupt status. the bits in the sist0 and sist1 indicate which scsi interrupt(s) occurred and determine what action is required to service the interrupt(s). 4. if only the dip bit is set, read dma status (dstat) to clear the interrupt condition and get the dma interrupt status. the bits in the dstat indicate which dma interrupt(s) occurred and determine what action is required to service the interrupt(s). 5. if both the sip and dip bits are set, read sist0, sist1, and dstat to clear the scsi and dma interrupt condition and get the interrupt status. if using 8-bit reads of the sist0, sist1, and dstat registers to clear interrupts, insert a 12 clk delay between the consecutive reads to ensure that the interrupts clear properly. both the scsi and dma interrupt conditions should be handled before leaving the interrupt service routine. it is recommended that the dma interrupt be serviced before the scsi interrupt because a serious dma interrupt condition could in?uence how the scsi interrupt is acted upon. 6. when using polled interrupts, go back to step 1 before leaving the interrupt service routine, in case any stacked interrupts moved in when the ?rst interrupt was cleared. when using hardware interrupts, the irq/ pin is asserted again if there are any stacked interrupts. this re-enters the system into the interrupt service routine.
chained block moves 2-39 2.11 chained block moves since the SYM53C895 has the capability to transfer 16-bit wide scsi data, a unique situation occurs when dealing with odd bytes. the chained move (chmov) scripts instruction along with the wide scsi send (wss) and wide scsi receive (wsr) bits in the scsi control two (scntl2) register facilitate these situations. figure 2.6 illustrates the chained block move instruction. figure 2.6 block move and chained block move instructions 00 04 08 0c 10 notes: chmov 5, 3 when data_out: moves ?ve bytes from address 03 in the host memory to the scsi bus (bytes 03, 04, 05, and 06 are moved and byte 07 remains in the low order byte of the scsi output data latch register and is married with the ?rst byte of the following move instruction). move 5, 9 when data_out: moves ?ve bytes from address 09 in the host memory to the scsi bus. 03 02 01 07 06 05 0b 0a 09 0f 0e 0d 13 12 11 00 04 08 0c 10 04 06 0b 0d 09 03 05 0a 0c 07 32 bits 16 bits
2-40 functional description 2.11.1 wide scsi send bit (wss) the wss bit is set whenever the scsi core is sending data (data out for initiator or data in for target), and the core detects a partial transfer at the end of a chained block move scripts instruction. note that this ?ag is not set if a normal block move instruction is used. under this condition, the scsi core does not send the low-order byte of the last partial memory transfer across the scsi bus. instead, the low-order byte is temporarily stored in the lower byte of the scsi output data latch (sodl) register and the wss ?ag is set. the hardware uses the wss ?ag to determine what behavior must occur at the start of the next data send transfer. when the wss ?ag is set at the start of the next transfer, the ?rst byte (the high-order byte) of the next data send transfer is married with the stored low-order byte in the sodl register; and the two bytes are sent out across the bus, regardless of the type of block move instruction (normal or chained). the ?ag is automatically cleared when the married word is sent. the ?ag is alternately cleared through scripts or by the microprocessor. additionally, the microprocessor or scripts can use this bit for error detection and recovery purposes. 2.11.2 wide scsi receive bit (wsr) the wsr bit is set whenever the scsi core is receiving data (data in for initiator or data out for target), and the core detects a partial transfer at the end of a block move or chained block move scripts instruction. when wsr is set, the high order byte of the last scsi bus transfer is not transferred to memory. instead, the byte is temporarily stored in the swide register. the hardware uses the wsr bit to determine what behavior must occur at the start of the next data receive transfer. the bit is automatically cleared at the start of the next data receive transfer. the microprocessor or scripts can alternatively clear this bit. additionally, the microprocessor or scripts can use this bit for error detection and recovery purposes. 2.11.3 scsi wide residue (swide) register this register stores data for partial byte data transfers. for receive data, the swide register holds the high-order byte of a partial scsi transfer which has not yet been transferred to memory. this stored data may be
chained block moves 2-41 a residue byte (and therefore ignored) or it may be valid data that is transferred to memory at the beginning of the next block move instruction. 2.11.4 scsi output data latch (sodl) register for send data, the low-order byte of the sodl register holds the low- order byte of a partial memory transfer which has not yet been transferred across the scsi bus. this stored data is usually married with the ?rst byte of the next data send transfer, and both bytes are sent across the scsi bus at the start of the next data send block move command. 2.11.5 chained block move scripts instruction a chained block move scripts instruction transfers consecutive data send or data receive blocks. using the chained block move instruction facilitates partial receive transfers and allows correct partial send behavior without additional op code overhead. behavior of the chained block move instruction varies slightly for sending and receiving data. for receive data (data in for initiator or data out for target), a chained block move instruction indicates that if a partial transfer occurred at the end of the instruction, the wsr ?ag is set.the high order byte of the last scsi transfer is stored in the scsi wide residue (swide) register rather than transferred to memory. the contents of the swide register should be the ?rst byte transferred to memory at the start of the chained block move data stream. since the byte count always represents data transfers to/from memory (as opposed to the scsi bus), the byte transferred out of the swide register is one of the bytes in the byte count. if the wsr bit is cleared when a receive data chained block move instruction is executed, the data transfer occurs similar to that of the regular block move instruction. whether the wsr bit is set or clear, when a normal block move instruction is executed, the contents of the swide register is ignored and the transfer takes place normally. for n consecutive wide data receive block move instructions, the 2nd through the nth block move instructions should be chained block moves.
2-42 functional description for send data (data out for initiator or data in for target), a chained block move instruction indicates that if a partial transfer terminates the chained block move instruction, the last low-order byte (the partial memory transfer) should be stored in the lower byte of the scsi output data latch (sodl) register and not sent across the scsi bus. without the chained block move instruction, the last low-order byte would be sent across the scsi bus. the starting byte count represents data bytes transferred from memory but not to the scsi bus when a partial transfer exists. for example, if the instruction is an initiator chained block move data out of ?ve bytes (and wss is not previously set), ?ve bytes are transferred out of memory to the scsi core, four bytes are transferred from the scsi core across the scsi bus, and one byte is temporarily stored in the lower byte of the sodl register waiting to be married with the ?rst byte of the next block move instruction. regardless of whether a chained block move or normal block move instruction is used, if the wss bit is set at the start of a data send command, the ?rst byte of the data send command is assumed to be the high-order byte and is married with the low-order byte stored in the lower byte of the sodl register before the two bytes are sent across the scsi bus. for n consecutive wide data send block move commands, the ?rst through the (nth - 1) block move instructions should be chained block moves.
symbios SYM53C895 pci to ultra2 scsi i/o processor 3-1 chapter 3 pci functional description this chapter describes the pci functional description for the SYM53C895 chip and includes these topics: section 3.1, pci addressing, page 3-1 section 3.2, pci bus commands and functions supported, page 3-2 section 3.3, pci cache mode, page 3-4 section 3.4, con?guration registers, page 3-10 3.1 pci addressing there are three types of pci-de?ned address spaces: 1. con?guration space 2. memory space 3. i/o space con?guration space is a contiguous 256 x 8-bit set of addresses dedicated to each slot or stub on the bus. decoding c_be/[3:0] determines if a pci cycle is intended to access con?guration register space. the idsel bus signal is a chip select that allows access to the con?guration register space only. a con?guration read/write cycle without idsel is ignored. the eight lower order addresses are used to select a speci?c 8-bit register. ad[10:8] are decoded as well, but they must be zero or the SYM53C895 does not respond. according to the pci speci?cation, ad[10:8] are to be used for multifunction devices. the host processor uses the pci con?guration space to initialize the SYM53C895. the lower 128 bytes of the SYM53C895 con?guration space holds system parameters while the upper 128 bytes map into the SYM53C895
3-2 pci functional description operating registers. for all pci cycles except con?guration cycles, the SYM53C895 registers are located on the 256-byte block boundary de?ned by the base address assigned through the con?gured register. the SYM53C895 operating registers are available in both the upper and lower 128-byte portions of the 256-byte space selected. at initialization time, each pci device is assigned a base address (in the case of the SYM53C895, the upper 24 bits of the address are selected) for memory accesses and i/o accesses. on every access, the SYM53C895 compares its assigned base addresses with the value on the address/data bus during the pci address phase. if there is a match of the upper 24 bits, the access is for the SYM53C895 and the low order eight bits de?ne the register to be accessed. a decode of c_be/ [3:0] determines which registers and what type of access is to be performed. pci de?nes memory space as a contiguous 32-bit memory address that is shared by all system resources, including the SYM53C895. base address register one determines which 256-byte memory area this device occupies. pci de?nes i/o space as a contiguous 32-bit i/o address that is shared by all system resources, including the SYM53C895. base address register zero determines which 256-byte i/o area this device occupies. 3.2 pci bus commands and functions supported bus commands indicate to the target the type of transaction the master is requesting. bus commands are encoded on the c_be/[3:0] lines during the address phase. pci bus command encoding and types appear in table 3.1 . the i/o read command reads data from an agent mapped in i/o address space. all 32 address bits are decoded. the i/o write command writes data to an agent when mapped in i/o address space. all 32 address bits are decoded. the memory read, memory read multiple, and memory read line commands read data from an agent mapped in memory address space. all 32 address bits are decoded.
pci bus commands and functions supported 3-3 the memory write and memory write and invalidate commands write data to an agent when mapped in memory address space. all 32 address bits are decoded. table 3.1 pci bus commands supported c_be[3:0] command type supported as master supported as slave 0b0000 special interrupt acknowledge no no 0b0001 special cycle no no 0b0010 i/o read cycle yes yes 0b0011 i/o write cycle yes yes 0b0100 reserved n/a n/a 0b0101 reserved n/a n/a 0b0110 memory read yes yes 0b0111 memory write yes yes 0b1000 reserved n/a n/a 0b1001 reserved n/a n/a 0b1010 con?guration read no yes 0b1011 con?guration write no yes 0b1100 memory read multiple yes 1 1. this operation is selectable by bit 2 in the dmode operating register no (defaults to 0b0110) 0b1101 dual address cycle no no 0b1110 memory read line yes 2 2. this operation is selectable by bit 3 in the dmode operating register. no (defaults to 0b0110) 0b1111 memory write and invalidate yes 3 3. this operation is selectable by bit 0 in the ctest3 operating register. no (defaults to 0b0111)
3-4 pci functional description 3.3 pci cache mode the SYM53C895 supports the pci speci?cation for an 8-bit cache line size register located in pci con?guration space. the cache line size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. in conjunction with the cache line size register, the pci commands memory read line, memory read multiple, and memory write and invalidate are each software enabled or disabled to allow the user full ?exibility in using these commands. 3.3.1 support for pci cache line size register the SYM53C895 supports the pci speci?cation for an 8-bit cache line size register in pci con?guration space. it can sense and react to nonaligned addresses corresponding to cache line boundaries. 3.3.2 selection of cache line size the cache logic selects a cache line size based on the values for the burst size in the dmode register, bit 2 in the ctest5 register, and the pci cache line size register. note: the SYM53C895 does not automatically use the value in the pci cache line size register as the cache line size value. the chip scales the value of the cache line size register down to the nearest binary burst size allowed by the chip (2, 4, 8, 16, 32, 64, or 128), compares this value to the burst size de?ned by the values of the dmode register and bit 2 of the ctest5 register, then selects the smallest as the value for the cache line size. the SYM53C895 uses this value for all burst data transfers. 3.3.3 alignment the SYM53C895 uses the calculated line size value to monitor the current address for alignment to the cache line size. when it is not aligned, the chip attempts to align to the cache boundary by using a smart aligning scheme. this means that it attempts to use the largest burst size possible that is less than the cache line size, to reach the
pci cache mode 3-5 cache boundary quickly with no over?ow. this process is a stepping mechanism that steps up to the highest possible burst size based on the current address. the stepping process begins at a 4-dword boundary. the SYM53C895 ?rst tries to align to a 4-dword boundary (0x0000, 0x0010, etc.) by using single dword transfers (no bursting). once this boundary has been reached the chip evaluates the current alignment to various burst sizes allowed, and selects the largest possible as the next burst size, while not exceeding the cache line size. the chip then issues this burst, and re- evaluates the alignment to various burst sizes, again selecting the largest possible while not exceeding the cache line size, as the next burst size. this stepping process continues until the chip reaches the cache line size boundary or runs out of data. once a cache line boundary is reached, the chip uses the cache line size as the burst size from then on, except in the case of multiples (explained below). the alignment process is ?nished at this point. example: cache line size - 16, current address = 0x01 C the chip is not aligned to a 4-dword cache boundary (the stepping threshold), so it issues four single-dword transfers (the ?rst is a 3-byte transfer). at address 0x10, the chip is aligned to a 4-dword boundary, but not aligned to any higher burst size boundaries that are less than the cache line size. so, the SYM53C895 issues a burst of 4. at this point, the address is 0x20, and the chip evaluates that it is aligned not only to a 4-dword boundary, but also to an 8-dword boundary. it selects the highest, 8, and bursts 8 dwords. at this point, the address is 0x40, which is a cache line size boundary. alignment stops, and the burst size from then on is switched to 16. 3.3.4 memory move misalignment the SYM53C895 does not operate in a cache alignment mode when a memory move instruction type is issued and the read and write addresses are different distances from the nearest cache line boundary. for example, if the read address is 0x21f, the write address is 0x42f, and the cache line size is eight (8), the addresses are byte aligned, but they are not the same distance from the nearest cache boundary. the read address is 1 byte from the cache boundary 0x220 and the write
3-6 pci functional description address is 17 bytes from the cache boundary 0x440. in this situation, the chip does not align to cache boundaries and operates as an sym53c825. 3.3.5 memory write and invalidate command the memory write and invalidate command is identical to the memory write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is, the master intends to write all bytes within the addressed cache line in a single pci transaction unless interrupted by the target. this command requires implementation of the pci cache line size register at address 0x0c in pci con?guration space. the SYM53C895 enables memory write and invalidate cycles when bit 0 in the ctest3 register (wrie) and bit 4 in the pci command register are set. this causes memory write and invalidate commands to be issued when the following conditions are met: 1. the clse bit, wrie bit, and pci con?guration command register bit 4 must be set. 2. the cache line size register must contain a legal burst size (2, 4, 8, 16, 32, 64, or 128) value and that value must be less than or equal to the dmode burst size. 3. the chip must have enough bytes in the dma fifo to complete at least one full cache line burst. 4. the chip must be aligned to a cache line boundary. when these conditions have been met, the SYM53C895 issues a memory write and invalidate command instead of a memory write command during all pci write cycles. 3.3.5.1 multiple cache line transfers the memory write and invalidate command can write multiple cache lines of data in a single bus ownership. the chip issues a burst transfer as soon as it reaches a cache line boundary. the size of the transfer is not automatically the cache line size, but rather a multiple of the cache line size as allowed for in the revision 2.1 of the pci speci?cation. the logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size being that determined from the dmode burst size bits and ctest 5, bit 2. if
pci cache mode 3-7 multiple cache line size transfers are not desired, the dmode burst size can be set to exactly the cache line size and the chip only issues single cache line transfers. after each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer and again selects the highest possible multiple of the cache line size, no larger than the dmode burst size. the most likely scenario of this scheme is that the chip selects the dmode burst size after alignment, and issues bursts of this size. the burst size, in effect, throttles down toward the end of a long memory move or block move transfer until only the cache line size burst size is left. the chip ?nishes the transfer with this burst size. 3.3.5.2 latency in accordance with the pci speci?cation, the chip's latency timer is ignored when issuing a memory write and invalidate command such that when a latency time-out has occurred, the SYM53C895 continues to transfer up until a cache line boundary is reached. at that point, the chip relinquishes the bus and ?nishes the transfer at a later time using another bus ownership. if the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached. 3.3.5.3 pci target retry during a write and invalidate transfer, if the target device issues a retry (stop with no trdy, indicating that no data was transferred), the SYM53C895 relinquishes the bus and immediately tries to ?nish the transfer on another bus ownership. the chip issues another memory write and invalidate command on the next ownership in accordance with the pci speci?cation. 3.3.5.4 pci target disconnect during a write and invalidate transfer, if the target device issues a disconnect the SYM53C895 relinquishes the bus and immediately tries to ?nish the transfer on another bus ownership. the chip does not issue another write and invalidate command on the next ownership unless the address is aligned.
3-8 pci functional description 3.3.5.5 memory read line command this command is identical to the memory read command, except that it additionally indicates that the master intends to fetch a complete cache line. this command is intended to be used with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading up to a cache line boundary rather than a single memory cycle. the read line mode function that exists in the previous sym53c8xx chips has been modi?ed in the SYM53C895 to re?ect the pci cache line size register speci?cations. the functionality of the enable read line bit (bit 3 in dmode) has been modi?ed to more resemble the write and invalidate mode in terms of conditions that must be met before a memory read line command is issued. however, the read line option operates exactly like the previous sym53c8xx chips when cache mode has been disabled by a clse bit reset or when certain conditions exist in the chip (explained below). the read line mode is enabled by setting bit 3 in the dmode register. if cache mode is disabled, read line commands are issued on every read data transfer, except op code fetches, as in previous sym53c8xx chips. if cache mode has been enabled, a read line command is issued on all read cycles, except op code fetches, when the following conditions have been met: 1. the clse and enable read line bits must be set. 2. the cache line size register must contain a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value must be less than or equal to the dmode burst size. 3. the number of bytes to be transferred at the time a cache boundary has been reached must be equal to or greater than the dmode burst size. 4. the chip must be aligned to a cache line boundary. when these conditions have been met, the chip issues a memory read line command instead of a memory read during all pci read cycles. otherwise, it issues a normal memory read command.
pci cache mode 3-9 3.3.6 memory read multiple command this command is identical to the memory read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. the SYM53C895 supports pci read multiple functionality and issues memory read multiple commands on the pci bus when the read multiple mode is enabled. this mode is enabled by setting bit 2 of the dmode register (ermp). if cache mode has been enabled, a memory read multiple command is issued on all read cycles, except op code fetches, when the following conditions have been met: 1. the clse and ermp bits must be set. 2. the cache line size register must contain a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value must be less than or equal to the dmode burst size. 3. the number of bytes to be transferred at the time a cache boundary has been reached must be at least twice the full cache line size. 4. the chip must be aligned to a cache line boundary. when these conditions have been met, the chip issues a memory read multiple command instead of a memory read during all pci read cycles. 3.3.6.1 burst size selection the memory read multiple command reads in multiple cache lines of data in a single bus ownership. the number of cache lines to be read is a multiple of the cache line size as allowed in the pci local bus speci?cation, revision 2.1 standard. the logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size being determined from the dmode burst size bits and ctest 5, bit 2. 3.3.6.2 read multiple with read line enabled when both the read multiple and read line modes have been enabled, the memory read line command is not issued if the above conditions are met. instead, a memory read multiple command is issued, even though the conditions for read line have been met.
3-10 pci functional description if the read multiple mode is enabled and the read line mode has been disabled, memory read multiple commands are still issued if the read multiple conditions are met. 3.3.6.3 unsupported pci commands the SYM53C895 does not respond to reserved commands, special cycle, dual address cycle, or interrupt acknowledge commands as a slave. it never generates these commands as a master. 3.4 con?guration registers the con?guration registers are accessible only by the system bios during pci con?guration cycles, and are not available to the user at any time. no other cycles, including scripts operations, can access these registers. the lower 128 bytes hold con?guration data while the upper 128 bytes hold the SYM53C895 operating registers, which are described in chapter 5, registers . these registers can be accessed by scripts or the host processor. note: the con?guration register descriptions provide general information only to indicate which pci con?guration addresses are supported in the SYM53C895. refer to the pci local bus speci?cation, revision 2 .1 for more detailed information.
book title 4-1 rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. draft xx/xx/xx chapter 4 signal descriptions this chapter presents the SYM53C895 pin con?gurations and signal de?nitions by using tables and illustrations. figure 4.1 is the functional signal grouping and figure 4.2 through figure 4.3 are the pin diagrams for the SYM53C895. table 4.1 and table 4.2 list the bga ball assignments by location and signal name. the pin de?nitions are in table 4.1 through table 4.12. these de?nitions are organized into the following functional groups: system, address/data, interface control, arbitration, error reporting, scsi, and optional interface. this chapter includes these main topics: section 4.1, voltage capabilities and limitations, page 4-3 section 4.2, internal pull-ups on SYM53C895 pins, page 4-4 section 4.3, pin descriptions, page 4-5 a slash (/) at the end of the signal name indicates that the active state occurs when the signal is at a low voltage. when the slash is absent, the signal is active at a high voltage.
draft xx/xx/xx 4-2 signal descriptions rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. figure 4.1 SYM53C895 functional signal grouping clk rst/ ad[31:0] c_be/[3:0] pa r frame/ trdy/ irdy/ stop/ devsel/ idsel req/ gnt/ serr/ perr/ sbsy srst ssel sreq sack satn/ smsg sclk sd[15:0/] sdp[1:0] gpio0 gpio1 gpio2 gpio3 mac/_testout irq/ big_lit diffsens testin gpio4 mwe/ mce/ moe mas0/ mas1/ mad[7:0] system address and data interface control arbitration error reporting scsi serial eeprom interface additional interface device local memory bus and control scd sio
draft xx/xx/xx voltage capabilities and limitations 4-3 rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. there are four signal type de?nitions: 1. i input, a standard input-only signal 2. o totem pole output, a standard output driver 3. t/s 3-state, a bidirectional, 3-state input/output pin 4. s/t/s sustained 3-state, an active low 3-state signal owned and driven by one and only one agent at a time 4.1 voltage capabilities and limitations the SYM53C895 uses 5 v biasing pins to allow the device to handle up to 5 v input voltage to the pci and external memory interface pins. when the SYM53C895 is used in a 5 v pci system, the biasing pins (v5bias(p)) must be supplied with 5 v. when they are used in a 3 v only pci environment, these biasing pins must be supplied with 3.3 v. the external memory pins (gpio pins and mad[7:0]) also use 5 volt- tolerant i/o pads. they also hav ea5v biasing pin (v5bias(m)). these pins should be supplied with 5 v when using 5 v memory devices, and with 3.3 v when using 3.3 v memory devices. the sclk input is also a 5 v tolerant input pin. the chip cannot operate normally if the 5 v biasing pins are grounded or disconnected. in addition, the pci biasing pins should not be shorted to the memory bias pin if mixed voltage environments (such as 5 v pci with 3 v memories) are possible. all other v dd supplies to the SYM53C895 must be set for 3.3 v operation. in addition, the chip only drives 3.3 v on any of the pins when they operate as outputs.
draft xx/xx/xx 4-4 signal descriptions rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. 4.2 internal pull-ups on SYM53C895 pins several pins on the SYM53C895 use internal pull-ups. table 4.1 describes the conditions under which these pull-ups are enabled or disabled. table 4.1 SYM53C895 internal pull-ups pin name pull-up current conditions for pull-up pci pins except irq, clk and rst 25 m a pull-ups enabled when and-tree mode is enabled by driving testin low irq 25 m a pull-up enabled when and-tree mode is enabled by driving testin low or when the irq mode bit (bit 3 of dcntl (0x3b)) is cleared 1 rst, clk n/a no pull-up mad [7:0] n/a no pull-ups mas/[1:0], mce/, moe/, mwe/ 25 m a pull-up enabled when and-tree mode is enabled by driving testin low or if the zmode bit (bit7 of ctest4 (0x21)) is set gpio[4:0] n/a no pull-ups scsi pads and sclk n/a no pull-ups rbias+, rbias- n/a no pull-ups diffsens n/a no pull-up, analog input protect pin big_lit/ 25 m a pull-up enabled when and-tree mode is enabled by driving testin low mac/_testout n/a no pull-up, output only test pin 82 25 m a pull-up all the time test pin 177 25 m a pull-up all the time testin 25 m a pull-up all the time test pins 180, 181, 182, 183 25 m a pull-up enabled when and-tree mode is enabled by driving testin low or if a hidden bit (bit7 of stest0 (0x4c)) is cleared (default = cleared) 1. when bit 3 of dcntl is set, the pad becomes a totem pole output pad and drives both high and low.
draft xx/xx/xx pin descriptions 4-5 rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. 4.3 pin descriptions table 4.2 SYM53C895 power and ground pins symbol 1 pin no. ball no. description v dd-pci 2 2, 13, 23, 26, 36, 46, 60, 197 (pins) power supplies to the pci i/o pins v ss-pci 2 8, 18, 31, 41, 56, 193, 200 (pins) power supplies to the pci i/o pins v dd-scsi 2 86, 96, 115, 125, 134, 144, 164, 174 (pins) power supplies to the scsi bus i/o pins v ss-scsi 2 91, 110, 120, 128, 131, 139, 151, 169 (pins) power supplies to the scsi bus i/o pins v dd-io 2 73, 81, 184 power supplies to the external memory interface v ss-io 2 78, 179 power supplies to the external memory interface v dd-core 64, 190 p17, r19, p2, p1 power supplies to the internal logic core v ss-core 68, 187 n18, p20, n1, m3 power supplies to the internal logic core v dd-a 85 h19 power pins used by analog circuitry note: the v dd-a pin is sensitive to noise above 90 mv at frequencies above 140 mhz. refer to ** for information on ?ltering schemes to protect this pin and the phase locked loop from high frequency noise. v ss-a 83 j18 power pins used by analog circuitry v5bias (pci) 4, 49 w18, y4 5-volt biasing pins for pci signals. these pins must be supplied with 5 v in a 5 v pci environment, or 3.3 v when used in a 3 v only pci environment.
draft xx/xx/xx 4-6 signal descriptions rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. note: if you apply separate power supplies to the v dd-io and v dd-core pins in a chip testing environment, either power up the pins simultaneously or power up v dd-core before v dd-io. the v dd-io pins must always power down before v dd-core. v5bias (mem) 62 t20 5 volt biasing pin for external memory interface signals. when using 5 v memory devices, this pin should be supplied with 5 v. when using 3.3 v memory devices, it should be supplied with 3.3 v. v dd f4, k4, r4, d6, u6, d11, u10, d15, u15, f17, l17, r17 power supplies v ss a1, d4, h4, n4, u4, d8, u8, j9 3 ,k9 3 ,l9 3 , m9 3 , j10 3 , k10 3 , l10 3 , m10 3 , j11 3 , k11 3 , l11 3 , m11 3 , j12 3 , k12 3 , l12 3 , m12 3 , d13, u13, d17, h17, n17, u17 power pins 1. all v dd pins must be supplied 3.3 v. the SYM53C895 output signals drive 3.3 v. 2. in the bga option, v dd-scsi ,v dd-pci and v dd-io are connected together and v ss-scsi ,v ss-pci , and v ss-io are connected together at package. 3. optional ground pins. table 4.2 SYM53C895 power and ground pins (cont.) symbol 1 pin no. ball no. description
draft xx/xx/xx pin descriptions 4-7 rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. table 4.3 system pins symbol pin no. ball no. type description clk 195 t1 i clock provides timing for all transactions on the pci bus and is an input to every pci device. all other pci signals are sampled on the rising edge of clk, and other timing parameters are de?ned with respect to this edge. this clock can optionally be used as the scsi core clock; however, the SYM53C895 is not able to achieve fast scsi-2 (or faster) transfer rates. rst/ 194 r2 i reset forces the pci sequencer of each device to a known state. all t/s and s/t/s signals are forced to a high impedance state, and all internal logic is reset. the rst/ input is synchronized internally to the rising edge of clk. the clk input must be active while rst/ is active to properly reset the device. table 4.4 address and data pins symbol pin no. ball no. type description ad[31:0] 199, 201C204, 3, 5, 6, 10C12, 14C17, 19, 33C35, 37C40, 42, 44, 45, 47, 48, 50, 51, 57, 58 u2, v1, v2, w1, v3, y3, v5, w5, w6, y6, v7, w7, y7, v8, w8, y8, v12, y13, w13, v13, y14, w14, y15, w15, y17, w17, v17, y19, v18, y18, v20 t/s physical long word address and data are multiplexed on the same pci pins. during the ?rst clock of a transaction, ad[31:0] contain a physical address. during subsequent clocks, ad[31:0] contain data. a bus transaction consists of an address phase, followed by one or more data phases. pci supports both read and write bursts. ad[7:0] de?ne the least signi?cant byte, and ad[31:24] de?ne the most signi?cant byte. c_be[3:0]/ 7, 20, 32, 43 y5, u9, w12, y16 t/s bus commands and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, c_be[3:0]/ de?ne the bus command. during the data phase, c_be[3:0]/ are used as byte enables. the byte enables determine which byte lanes carry meaningful data. c_be0/ applies to byte 0, and c_be3/ applies to byte 3. pa r 3 0 y12 t/s parity is the even parity bit that protects the ad[31:0] and c_be[3:0]/ lines. during address phase, both the address and command bits are covered. during data phase, both data and byte enables are covered.
draft xx/xx/xx 4-8 signal descriptions rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. table 4.5 interface control pins symbol pin no. ball no. type description frame/ 21 v9 s/t/s cycle frame is driven by the current master to indicate the beginning and duration of an access. frame/ is asserted to indicate a bus transaction is beginning. while frame/ is asserted, data transfers continue. when frame/ is deasserted, the transaction is in the ?nal data phase or the bus is idle. trdy/ 24 w10 s/t/s target ready indicates the selected devices ability to complete the current data phase of the transaction. trdy/ is used with irdy/. a data phase is completed on any clock when both trdy/ and irdy/ are sampled asserted. during a read, trdy/ indicates that valid data is present on ad[31:0]. during a write, it indicates the target is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together. irdy/ 22 w9 s/t/s initiator ready indicates the bus masters ability to complete the current data phase of the transaction. this signal is used with trdy/. a data phase is completed on any clock when both irdy/ and trdy/ are sampled asserted. during a write, irdy/ indicates that valid data is present on ad[31:0]. during a read, it indicates the master is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together. stop/ 27 w11 s/t/s stop indicates that the selected target is requesting the master to stop the current transaction. devsel/ 25 y10 s/t/s device select indicates that the driving device has decoded its address as the target of the current access. as an input, it indicates to a master whether any device on the bus has been selected. idsel 9 v6 i initialization device select is used as a chip select in place of the upper 24 address lines during con?guration read and write transactions.
draft xx/xx/xx pin descriptions 4-9 rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. table 4.6 arbitration pins symbol pin no. ball no. type description req/ 198 u1 o request indicates to the arbiter that this agent desires use of the pci bus. this is a point to point signal. every master has its own req/. gnt/ 196 t2 i grant indicates to the agent that access to the pci bus has been granted. this is a point to point signal. every master has its own gnt/. table 4.7 error reporting pins symbol pin no. ball no. type description perr/ 28 v11 s/t/s parity error may be pulsed active by an agent that detects a data parity error. perr/ can be used by any agent to signal data corruptions. serr/ 29 u11 o this open drain output pin reports address parity errors. on detection of a perr/ pulse, the central resource may generate a nonmaskable interrupt to the host cpu, which often implies the system is unable to continue operation once error processing is complete.
draft xx/xx/xx 4-10 signal descriptions rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. table 4.8 scsi pins, lvd link mode symbol pin no. ball no. type description sclk 80 j20 i sclk derives all scsi-related timings. the speed of this clock is determined by the application requirements; in some applications sclk may be sourced internally from the pci bus clock (clk). if sclk is internally sourced, then the sclk pin should be tied low. for ultra2 scsi operation, this pin must be connected to an external 40 mhz oscillator, used with the internal clock quadrupler. sd - [15:0], sdp - [1:0] 167, 170, 172, 175, 87, 89, 92, 94, 135, 137, 140, 142, 145, 147, 149, 162, 165, 132 f2, g2, h2, j3, g20, f20, e20, d20, a9, a8, a7, b6, b5, b4, b3, c1, e1, b10 i/o negative half of lvd link signal pair for scsi data lines. scsi data includes the following data lines and parity signals: sd[15:0]/(16-bit scsi data bus), and sdp[1:0]/(scsi data parity bits). sd+[15:0], sdp+[1:0] 168, 171, 173, 176, 88, 90, 93, 95, 136, 138, 141, 143, 146, 148, 150, 163, 166, 133 f1, g1, h1, j2, g19, f19, e19, d19, b9, b8, b7, a5, a4, a3, b2, d1, f3, c10 i/o positive half of lvd link signal pair for scsi data lines. sctrl - 111, 97, 116, 99, 121, 123, 126, 118, 113 c17, c20, b16, d18, b14, b13, b12, b15, a18 i/o negative half of lvd link signal pair for scsi control, which includes the following signals: scd - scsi phase line, command/data sio - scsi phase line, input/output smsg - scsi phase line, message sreq - data handshake signal from target device sack - data handshake signal from initiator device sbsy - scsi bus arbitration signal, busy satn - scsi attention, the initiator is requesting a message out phase srst - scsi bus reset ssel - scsi bus arbitration signal, select device
draft xx/xx/xx pin descriptions 4-11 rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. sctrl+ 112, 98, 117, 100, 122, 124, 127, 119, 114 d16, e17, a16, c19, a14, a13, a12, a15, a17 i/o positive half of lvd link signal pair for scsi control, which includes the following signals: scd+ scsi phase line, command/data sio+ scsi phase line, input/output smsg+ scsi phase line, message sreq+ data handshake signal from target device sack+ data handshake signal from initiator device sbsy+ scsi bus arbitration signal, busy satn+ scsi attention, the initiator is requesting a message out phase srst+ scsi bus reset ssel+ scsi bus arbitration signal, select device rbias+, rbias - 130, 129 a10, a11 i used to connect an external resistor to generate the bias current used by lvd link pads. diffsens 84 h20 i the differential sense pin detects the voltage level of an incoming scsi signal to determine whether it is from a single-ended, lvd, or hvd device. the result is displayed in stest4 bits[7:6]. when external differential transceivers are used and a high level is detected on this pin, all chip scsi outputs are 3-stated to avoid damage to the transceivers. this pin should be connected to the diffsens signal on the scsi cable. note: the maximum voltage allowed to this pin is 3.3-volts. table 4.8 scsi pins, lvd link mode (cont.) symbol pin no. ball no. type description
draft xx/xx/xx 4-12 signal descriptions rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. table 4.9 scsi pins, single-ended mode symbol pin no. ball no. type description sclk 80 j20 i sclk derives all scsi-related timings. the speed of this clock is determined by the application requirements; in some applications sclk may be sourced internally from the pci bus clock (clk). if sclk is internally sourced, then the sclk pin should be tied low. sd - [15:0], sdp - [1:0] 167, 170, 172, 175, 87, 89, 92, 94, 135, 137, 140, 142, 145, 147, 149, 162, 165, 132 f2, g2, h2, j3, g20, f20, e20, d20, a9, a8, a7, b6, b5, b4, b3, c1, e1, b10 i/o scsi data includes the following data lines and parity signals: sd[15:0]/(16-bit scsi data bus), and sdp[1:0]/(scsi data parity bits). sd+[15:0], sdp+[1:0] 168, 171, 173, 176, 88, 90, 93, 95, 136, 138, 141, 143, 146, 148, 150, 163, 166, 133 f1, g1, h1, j2, g19, f19, e19, d19, b9, b8, b7, a5, a4, a3, b2, d1, f3, c10 o these signals drive 0-volts. sctrl - 111, 97, 116, 99, 121, 123, 126, 118, 113 c17, c20, b16, d18, b14, b13, b12, b15, a18 i/o scsi control, includes the following signals: scd - scsi phase line, command/data sio - scsi phase line, input/output smsg - scsi phase line, message sreq - data handshake signal from target device sack - data handshake signal from initiator device sbsy - scsi bus arbitration signal, busy satn - scsi attention, the initiator is requesting a message out phase srst - scsi bus reset ssel - scsi bus arbitration signal, select device
draft xx/xx/xx pin descriptions 4-13 rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. sctrl+ 112, 98, 117, 100, 122, 124, 127, 119, 114 d16, e17, a16, c19, a14, a13, a12, a15, a17 o these pins drive 0 volts. diffsens 84 h20 i the differential sense pin detects the voltage level of an incoming scsi signal to determine whether it is from a single-ended, lvd, or hvd device. the result is displayed in stest4 bits [7:6]. when external differential transceivers are used and a high level is detected on this pin, all chip scsi outputs are 3-stated to avoid damage to the transceivers. this pin should be connected to the diffsens signal on the scsi cable. note: the maximum voltage allowed to this pin is 3.3 volts. table 4.9 scsi pins, single-ended mode (cont.) symbol pin no. ball no. type description
draft xx/xx/xx 4-14 signal descriptions rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. table 4.10 scsi pins, high voltage differential mode symbol pin no. ball no. type description sclk 80 j20 i sclk derives all scsi-related timings. the speed of this clock is determined by the application requirements; in some applications sclk may be sourced internally from the pci bus clock (clk). if sclk is internally sourced, then the sclk pin should be tied low. sd - [15:0] sdp - [1:0] 167, 170, 172, 175, 87, 89, 92, 94, 135, 137, 140, 142, 145, 147, 149, 162, 165, 132 f2, g2, h2, j3, g20, f20, e20, d20, a9, a8, a7, b6, b5, b4, b3, c1, e1, b10 i/o scsi data lines. scsi data includes the following data lines and parity signals: sd[15:0]/(16-bit scsi data bus), and sdp[1:0]/ (scsi data parity bits). sd+[15:0] sdp+[1:0] 168, 171, 173, 176, 88, 90, 93, 95, 136, 138, 141, 143, 146, 148, 150, 163, 166, 133 f1, g1, h1, j2, g19, f19, e19, d19, b9, b8, b7, a5, a4, a3, b2, d1, f3, c10 o driver direction control for scsi data lines.
draft xx/xx/xx pin descriptions 4-15 rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. sctrl - 111, 97, 116, 99, 121, 123, 126, 118, 113 c17, c20, b16, d18, b14, b13, b12, b15, a18 i/o scsi control includes these signals: scd - scsi phase line, command/data sio - scsi phase line, input/output smsg - scsi phase line, message sreq - data handshake signal from target device sack - data handshake signal from initiator device sbsy - scsi bus arbitration signal, busy satn - scsi attention, the initiator is requesting a message out phase srst - scsi bus reset ssel - scsi bus arbitration signal, select device sctrl+ 112, 98, 117, 100, 122, 124, 127, 119, 114 d16, e17, a16, c19, a14, a13, a12, a15, a17 o driver direction control for the external transceivers, which includes the following signals: sreq+ data handshake signal from target device sack+ data handshake signal from initiator device sbsy+ scsi bus arbitration signal, busy srst+ scsi bus reset ssel+ scsi bus arbitration signal, select device note: for hvd operation, scd+, sio+, smsg+, and satn+ are not used. diffsens 84 h20 1 the differential sense pin detects the voltage level of an incoming scsi signal to determine whether it is from a single-ended, lvd, or hvd device. the result is displayed in stest4 bits [7:6]. when external differential transceivers are used and a high level is detected on this pin, all chip scsi outputs are 3-stated to avoid damage to the transceivers. this pin should be connected to the diffsens signal on the scsi cable. note: the maximum voltage allowed to this pin is 3.3 volts. table 4.10 scsi pins, high voltage differential mode (cont.) symbol pin no. ball no. type description
draft xx/xx/xx 4-16 signal descriptions rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. table 4.11 additional pins symbol pin no. ball no. type description testin 178 k2 i test in. when this pin is driven low, the SYM53C895 connects all inputs and outputs to an and tree. all scsi control signals and data lines are connected to the and tree. the output of the and tree is connected to the testout pin. this allows manufacturers to verify chip connectivity and determine exactly which pins are not properly attached. when the testin pin is driven low, internal pull-ups are enabled on all input, output, and bidirectional pins, all outputs and bidirectional signals are 3-stated, and the mac/_testout pin is enabled. connectivity can be tested by driving one of the SYM53C895 pins low. the mac/_testout pin should respond by also driving low. gpio0_ fetch/ 61 t19 i/o general purpose i/o pin. optionally, when driven low, this pin indicates that the next bus request is for an op code fetch. this pin powers up as a general purpose input.this pin has two speci?c purposes in the symbios software. the software uses it to toggle scsi device leds, turning on the led whenever the SYM53C895 is on the scsi bus. the software drives this pin low to turn on the led, or drives it high to turn off the led. this signal can also be used as data i/o for serial eeprom access. in this case, it is used with the gpio1 pin, which serves as a clock. gpio1_ master/ 63 r18 i/o general purpose i/o pin. optionally, when driven low, this pin indicates that the SYM53C895 is bus master. this pin powers up as a general purpose input. symbios software supports use of this signal in serial eeprom applications, when enabled, in combination with the gpio0 pin. when this signal is used as a clock for serial eeprom access, the gpio0 pin serves as data. gpio[4:2] 67C65 p19 p18 r20 i/o general purpose i/o pins. gpio4 powers up as an output. symbios software also supports use of this signal as the enable line for v pp , the 12 volt power supply to the external ?ash memory interface. gpio[3:2] power up as inputs. mac/_ testout 79 k19 t/s memory access control. this pin can be programmed to indicate local or system memory accesses (non-pci applications). it is also used to test the connectivity of the SYM53C895 signals using and tree scheme. the mac/_testout pin is only driven as the test out function when the testin/ pin is driven low.
draft xx/xx/xx pin descriptions 4-17 rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. irq/ 59 u20 o interrupt. this signal, when asserted low, indicates that an interrupting condition has occurred and that service is required from the host cpu. the output drive of this pin is programmed as either open drain with an internal weak pull- up or, optionally, as a totem pole driver. refer to the description of the dcntl register, bit 3, for additional information. big_lit/ 192 p3 i big_little endian select. when this pin is driven low, the SYM53C895 routes the ?rst byte of an aligned scsi to pci transfer to byte lane zero of the pci bus and subsequent bytes received are routed to ascending lanes. an aligned pci to scsi transfer routes pci byte lane zero onto the scsi bus ?rst, and transfer ascending byte lanes in order. when this pin is driven high, the SYM53C895 routes the ?rst byte of an aligned scsi to pci transfer to byte lane three of the pci bus and subsequent bytes received are routed to descending lanes. an aligned pci to scsi transfer routes pci byte lane three onto the scsi bus ?rst and transfer descending byte lanes in order. this mode of operation also applies to the external memory interface. when this pin is driven in little endian mode and the chip is performing a read from external memory, the byte of data accessed at location 0x00000 is routed to pci byte lane zero and the data accessed at location 0x00003 is routed to pci byte lane three. when the chip is performing a write to ?ash memory, pci byte lane zero is routed to location 0x00000 and ascending byte lanes are routed to subsequent memory locations. when this pin is driven in big endian mode and the chip is performing a read from external memory, the byte of data accessed at location 0x00000 is routed to pci byte lane three and the data accessed at location 0x00003 is routed to byte lane zero. when the chip is performing a write to ?ash memory, pci byte lane three is routed to location 0x00000 and descending byte lanes are routed to subsequent memory locations. test pins 82, 177, 180, 181, 182, 183 j1, j19, k1, l1, l2, l3 i/o lsi logic uses test pins for diagnostic testing. these pins should not be used in actual system design; they must be left ?oating or pulled high. table 4.11 additional pins (cont.)
draft xx/xx/xx 4-18 signal descriptions rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. table 4.12 external memory interface pins symbol pin no. ball no. type description mas0/ 186 m2 o memory address strobe 0. this pin latches in the least signi?cant address byte of an external eeprom or ?ash memory. since the SYM53C895 moves addresses eight bits at a time, this pin connects to the clock of an external bank of ?ip-?ops that assemble up to a 20-bit address for the external memory. mas/1 185 m1 o memory address strobe 1. this pin latches in the address byte corresponding to address bits [15:8] of an external eeprom or ?ash memory. since the SYM53C895 moves addresses eight bits at a time, this pin connects to the clock of an external bank of ?ip-?ops that assemble up to a 20-bit address for the external memory. mad[7:0] see individual pin descriptions the mad[7:0] pins form the memory address/data bus. this bus is used in conjunction with the memory address strobe pins and external address latches to assemble up to a 20-bit address for an external eeprom or ?ash memory. this bus puts out the most signi?cant byte ?rst and ?nishes with the least signi?cant byte. it also writes data to a ?ash memory or read data into the chip from external eeprom or ?ash memory. the eight signals on the mad bus have speci?c functions. refer to the individual pin descriptions below. mad[7:6] 69C70 n19, n20 i/o mad[7:6] enable different power-up options related to the external serial eeprom interface. these options are programmed by connecting a 4.7 k w resistor between the appropriate mad pin and v ss . for more information, refer to the serial eeprom interface section in chapter 2 and the subsystem id/subsystem vendor id register descriptions in chapter 3 . 00 vendor speci?c information is automatically downloaded from the serial eeprom through gpio0 (clock) and gpio1 (data) and loaded into pci con?guration registers 0x2cC0x2f 01 reserved 10 no download is performed, however, the pci con?guration registers 0x2cC0x2f are now writable. 11 vendor-speci?c information is automatically downloaded from the eeprom through gpio0 (data) and gpio1 (clock) and loaded into pci con?guration registers 0x2cC0x2f.
draft xx/xx/xx pin descriptions 4-19 rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved. mad5 71 m18 i/o the mad5 pin enables/disables the 4 kbytes of internal ram on the SYM53C895. pull this pin high to enable the scripts ram (default), and pull it low (with a 4 k w resistor) to disable the scripts ram. mad4 72 m19 i/o the mad4 pin is reserved and should be pulled up. it may be used by lsi logic in future devices. mad[3:1] 74C76 m20, l19, l20, i/o the mad[3:1] pins set the size of the external parallel rom device attached to the SYM53C895. encoding for these pins is listed below (0 indicates a pull-down resistor is attached, 1 indicates a pull-up resistor is attached). 000 16 kbytes 001 32 kbytes 010 64 kbytes 011 128 kbytes 100 256 kbytes 101 512 kbytes 110 1024 kbytes 111 no external memory present mad0 77 k20 i/o mad0 is the slow rom pin. when pulled down, it enables two extra clock cycles of data access time. this accommodates a 200 ns memory device on the mad bus. when the pin is high, a 150 ns or faster memory device must be used. mwe/ 188 n2 o memory write enable. this pin writes the enable signal to an external ?ash memory. moe/ 189 n3 o memory output enable. this pin is used as an output enable signal to an external eeprom or ?ash memory during read operations. mce/ 191, r1 o memory chip enable. this pin is used as a chip enable signal to an external eeprom or ?ash memory device. table 4.12 external memory interface pins (cont.)
draft xx/xx/xx 4-20 signal descriptions rev. letter copyright ? 1999 by lsi logic corporation. all rights reserved.
symbios sym53c896 pci to dual channel ultra2 scsi multifunction controller 5-1 chapter 5 registers this chapter contains descriptions of the pci registers and the SYM53C895 operating registers. the terms set and assert refer to bits that are programmed to a binary one. similarly, the terms deassert, clear and reset refer to bits that are programmed to a binary zero. reserved bit functions may be changed at any time. these bits should never be set by the user. unless otherwise indicated, all bits in registers are active high, which means the feature is enabled by setting the bit. the bottom row of every register diagram shows the default register values that are enabled after the chip is powered on or reset. this chapter includes these topics: section 5.1, pci con?guration registers, page 5-1 section 5.2, scsi registers, page 5-15 5.1 pci con?guration registers table 5.1 shows the pci con?guration registers implemented by the SYM53C895. addresses 0x40 through 0x7f are not de?ned. all pci-compliant devices, such as the SYM53C895, must support the vendor id, device id, command, and status registers. support of other pci-compliant registers is optional. in the SYM53C895, registers that are not supported are not writable and return all zeroes when read. only those registers and bits that are currently supported by the SYM53C895 are described in this chapter. for more detailed information on pci registers, please see the pci local bus speci?cation, revision 2.1 .
5-2 registers table 5.1 pci con?guration register map 31 16 15 0 device id vendor id 0x00 status command 0x04 class code revision id (rev id) 0x08 not supported header type latency timer cache line size 0x0c base address zero (i/o) 1 1. i/o base is supported. 0x10 base address one (memory) 2 2. memory base is supported. 0x14 ram base address 3 3. this register powers up enabled and can be disabled by pull-down resistors on the mad5 pin. 0x18 not supported 0x1c not supported 0x20 not supported 0x24 reserved 0x28 subsystem id subsystem vendor id 0x2c expansion rom base address 4 4. if expansion memory is enabled through pull-down resistors on the mad[7:0] bus. 0x30 reserved 0x34 reserved 0x38 max_lat min_gnt interrupt pin interrupt line 0x3c 5 5. addresses 0x40 to 0x7f are not de?ned. all unsupported registers are not writable and return all zeros when read. reserved registers also return zeros when read.
pci con?guration registers 5-3 register: 0x00C0x01 vendor id read only vid[15:0] vendor id [15:0] this 16-bit register identi?es the manufacturer of the device. the vendor id is 0x1000. register: 0x02C0x03 device id read only did[15:0] device id [15:0] this 16-bit register identi?es the particular device. the SYM53C895 device id is 0x000c. register: 0x04C0x05 command read/write the scsi command register provides coarse control over a devices ability to generate and respond to pci cycles. when a zero is written to this register, the SYM53C895 is logically disconnected from the pci bus for all accesses except con?guration accesses. 15 0 vid[15:0] 0001000000000000 15 0 did[15:0] 0000000000000011 15 9 8 7 6 5 4 3 2 1 0 r se r eper r wie r ebm ems eis xxxxxxx0x 0 x0x 0 0 0
5-4 registers r reserved [15:9] se serr/ enable 8 this bit enables the serr/ driver. serr/ is disabled when this bit is cleared. the default value of this bit is zero. this bit and bit 6 must be set to report address parity errors. r reserved 7 eper enable parity error response 6 this bit allows the SYM53C895 to detect parity errors on the pci bus and report these errors to the system. only data parity checking is enabled and disabled with this bit. the SYM53C895 always generates parity for the pci bus. r reserved 5 wie write and invalidate enable 4 this bit allows the SYM53C895 to generate write and invalidate commands on the pci bus. the wie bit in the dma control (dcntl) register must also be set for the device to generate memory write and invalidate commands. r reserved 3 ebm enable bus mastering 2 this bit controls the ability of the SYM53C895 to act as a master on the pci bus. a value of zero disables this device from generating pci bus master accesses. a value of one allows the SYM53C895 to behave as a bus master. the device must be a bus master in order to fetch scripts instructions and transfer data. ems enable memory space 1 this bit controls the ability of the SYM53C895 to respond to memory space accesses. a value of zero (0) disables the device response. a value of one (1) allows the SYM53C895 to respond to memory space accesses at the address range speci?ed by the base address one (memory) and ram base address registers in the pci con?guration space.
pci con?guration registers 5-5 eis enable i/o space 0 this bit controls the SYM53C895 response to i/o space accesses. a value of zero disables the device response. a value of one allows the SYM53C895 to respond to i/o space accesses at the address range speci?ed by the base address register zero (i/o) register in the pci con?guration space. register: 0x06C0x07 status read/write reads to this register behave normally. writes are slightly different in that bits can be cleared, but not set. a bit is cleared whenever the register is written, and the data in the corresponding bit location is a one. for instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. dpe detected parity error (from slave) 15 this bit is set by the SYM53C895 whenever it detects a data parity error, even if data parity error handling is disabled. sse signaled system error 14 this bit is set whenever the device asserts the serr/ signal. rma received master abort (from master) 13 a master device should set this bit whenever its transaction (except for special cycle) is terminated with master abort. rta received target abort (from master) 12 a master device should set this bit whenever its transaction is terminated by target abort. 15 14 13 12 11 10 9 8 7 5 4 3 0 dpe sse rma rta r dt[1:0] dpp r nc r 0000x000xxx1xxxx
5-6 registers r reserved 11 dt[10:9] devsel/ timing [10:9] these bits encode the timing of devsel/. these are encoded as: these bits are read-only and should indicate the slowest time that a device asserts devsel/ for any bus command except con?guration read and con?guration write. the SYM53C895 supports a value of 0b01. dpr data parity error reported 8 this bit is set when the following conditions are met: the bus agent asserted perr/ itself or observed perr/ asserted; the agent setting this bit acted as the bus master for the operation in which the error occurred and; the parity error response bit in the command register is set. r reserved [7:0] register: 0x08 revision id (rev id) read only rid[7:0] revision id [7:0] this register speci?es a device speci?c revision identi?er. the upper nibble is always set to 0x0000. the lower nibble re?ects the current revision level of the device. it should have the same value as the chip revision level bits in the ctest3 register. 0b00 fast 0b01 medium 0b10 slow 0b11 reserved. 7 0 rid[7:0] 0000xxxx
pci con?guration registers 5-7 register: 0x09C0x0b class code read only cc[23:0] class code [23:0] this 24-bit register identi?es the generic function of the device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identi?es a speci?c register-level programming interface. the value of this register is 0x010000, which identi?es a scsi controller. register: 0x0c cache line size read/write cls[7:0] cache line size [7:0] this register speci?es the system cache line size in units of 32-bit words. cache mode is enabled and disabled by the cache line size enable (clse) bit, bit 7 in the dcntl register. setting this bit causes the SYM53C895 to align to cache line boundaries before allowing any bursting, except during memory moves in which the read and write addresses are not aligned to a burst size boundary. for more information on this register, see section 3.3.1, support for pci cache line size register . 23 0 cc[23:0] 000000010000000000000000 7 0 cls[7:0] 00000000
5-8 registers register: 0x0d latency timer read/write lt[7:0] latency timer [7:0] the latency timer register speci?es, in units of pci bus clocks, the value of the latency timer for this pci bus master. the scsi functions of the SYM53C895 support this timer. all eight bits are writable, allowing latency values of 0C255 pci clocks. use the following equation to calculate an optimum latency value for the scsi functions of the SYM53C895. latency = 2 + (burst size * (typical wait states + 1)) values greater than optimum are also acceptable. register: 0x0e header type read only ht[7:0] header type [7:0] this 8-bit register identi?es the layout of bytes 0x10 through 0x3f in the con?guration space and also whether or not the device contains multiple functions. the value of this register is 0x00. 7 0 lt[7:0] 00000000 7 0 ht[7:0] 00000000
pci con?guration registers 5-9 register: 0x10C0x13 base address register zero (i/o) read/write barz[31:0] base address register zero - i/o [31:0] this 32-bit base address register maps the operating register set into i/o space. bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into i/o space. for detailed information on the operation of this register, refer to the pci local bus speci?cation, revision 2.1. register: 0x14C0x17 base address one (memory) read/write baro[31:0] base address one - memory [31:0] this 32-bit base address register maps the operating register set into memory space. bit 0 is hardwired to zero. for detailed information on the operation of this register, refer to the pci local bus speci?cation, revision 2.1 . 31 0 barz[31:0] 00000000000000000000000000000000 31 0 baro[31:0] 00000000000000000000000000000000
5-10 registers register: 0x18C0x1b ram base address read/write ramba[31:0] ram base address [31:0] this 32-bit base address register holds the memory base address of the 4 kbytes internal ram. the user can read this register through the scratchb register in the operating register set when bit 3 of the ctest2 register is set. register: 0x1cC0x1f not supported register: 0x20C0x23 not supported register: 0x24C0x27 not supported register: 0x28C0x31 reserved register: 0x2cC0x2d subsystem vendor id read only svid[15:0] subsystem vendor id [15:0] this 16-bit register uniquely identi?es the vendor manufacturing the add-in board or subsystem where this pci device resides. it provides a mechanism for an add-in card vendor to distinguish its cards from another 31 0 ramba[31:0] 00000000000000000000000000000000 15 0 svid[15:0] 0000000000000000
pci con?guration registers 5-11 vendor cards, even if the cards have the same pci controller installed on them (and therefore the same vendor id and device id). if the external serial eeprom interface is enabled, this register is automatically loaded at power-up from the external serial eeprom and contains the value down- loaded from the serial eeprom or a value of 0x0000 if the download fails. all of the bits in this register are cleared if serial eeprom access is not enabled. the 16-bit value that should be stored in the external serial eeprom for this register is the vendor pci vendor id and must be obtained from the pci special interest group (sig). refer to section 2.6.2, serial eeprom interface for more information on downloading a value for this register. register: 0x2eC0x2f subsystem id read only sid[15:0] subsystem id [15:0] this 16-bit register uniquely identi?es the add-in board or subsystem where the SYM53C895 resides. it provides a mechanism for an add-in card vendor to distinguish between its cards that use the same pci controller installed on them (and therefore the same vendor id and device id). if the external serial eeprom interface is enabled, this register is automatically loaded at power-up from the external serial eeprom and contains the value down- loaded from the serial eeprom or a value of 0x0000 if the download fails. all of the bits in this register are cleared if the serial eeprom access is not enabled. refer to section 2.6.2, serial eeprom interface for additional information on downloading a value for this register. 15 0 sid[15:0] 0000000000000000
5-12 registers in some operating system implementations, bit 15 of this register indicates whether the SYM53C895 is being controlled by symbios software or by a different device driver. a value of 0 indicates that the symbios software controls the chip, and a value of 1 indicates another driver. register: 0x30C0x33 expansion rom base address read/write erba[31:0] expansion rom base address [31:0] this four-byte register handles the base address and size information for the expansion rom. it functions exactly like the base address register zero (i/o) and base address one (memory) registers, except that the encoding of the bits is different. the upper 21 bits correspond to the upper 21 bits of the expansion rom base address. the expansion rom enable bit, bit 0, is the only bit de?ned in this register. this bit controls whether or not the device accepts accesses to its expansion rom. when the bit is set, address decoding is enabled, and a device is used with or without an expansion rom depending on the system con?guration. to access the external memory interface, also set the memory space bit in the command register. the host system detects the size of the external memory by ?rst writing the expansion rom base address register with all ones and then reading back the register. the scsi functions of the SYM53C895 respond with zeros in all dont care locations. the ones in the remaining bits represent the binary version of the external memory size. for example, to indicate an external memory size of 32 kbytes, this register, when written with ones and read back, returns ones in the upper 17 bits. 31 0 erba[31:0] 00000000000000000000000000000001
pci con?guration registers 5-13 register: 0x34-0x3b reserved register: 0x3c interrupt line read/write il[7:0] interrupt line [7:0] this register communicates interrupt line routing information. post software writes the routing information into this register as it con?gures the system. the value in this register tells which input of the system interrupt controller(s) the device interrupt pin is connected to. val- ues in this register are speci?ed by system architecture. register: 0x3d interrupt pin read only ip[7:0] interrupt pin [7:0] this register speci?es the interrupt pin that the device uses. its value is set to 0x01 for the inta/ signal. 7 0 il[7:0] 00000000 7 0 ip[7:0] 00000001
5-14 registers register: 0x3e min_gnt read only mg[7:0] min_gnt [7:0] this register speci?es the desired settings for latency timer values. min_gnt speci?es how long a burst period the device needs. the value speci?ed in these registers is in units of 0.25 microseconds. the SYM53C895 sets this register to 0x11. register: 0x3f max_lat read only ml[7:0] max_lat [7:0] this register speci?es the desired settings for latency timer values. max_lat speci?es how often the device needs to gain access to the pci bus. the value speci?ed in these registers is in units of 0.25 microseconds. the SYM53C895 scsi function sets this register to 0x40. 7 0 mg[7:0] 00010001 7 0 ml[7:0] 01000000
scsi registers 5-15 5.2 scsi registers table 5.2 , the register map, lists registers by operating address. note: the only register that the host cpu can access while the SYM53C895 is executing scripts is the istat register. attempts to access other registers interferes with the operation of the chip. however, all operating registers are accessible with scripts. all read data is synchronized and stable when presented to the pci bus. note: the SYM53C895 cannot fetch scripts instructions from the operating register space. instructions must be fetched from system memory or the internal scripts ram.
5-16 registers table 5.2 scsi register map scntl3 scntl2 scntl1 scntl0 0x00 gpreg sdid sxfer scid 0x04 sbcl ssid socl sfbr 0x08 sstat2 sstat1 sstat0 dstat 0x0c dsa 0x10 reserved istat 0x14 ctest3 ctest2 ctest1 reserved 0x18 temp 0x1c ctest6 ctest5 ctest4 dfifo 0x20 dcmd dbc 0x24 dnad 0x28 dsp 0x2c dsps 0x30 scratch a 0x34 dcntl sbr dien dmode 0x38 adder 0x3c sist1 sist0 sien1 sien0 0x40 gpcntl macntl swide slpar 0x44 rpid1 rpid0 stime1 stime0 0x48 stest3 stest2 stest1 stest0 0x4c reserved stest4 sidl 0x50 reserved sodl 0x54 reserved sbdl 0x58 scratch b 0x5c scratchc 0x60 scratchd 0x64 scratche 0x68 scratchf 0x6c scratchg 0x70 scratchh 0x74 scratchi 0x78 scratchj 0x7f
scsi registers 5-17 register: 0x00 scsi control zero (scntl0) read/write arb1[1:0] arbitration mode bits 1 and 0 [7:6] simple arbitration 1. the SYM53C895 waits for a bus free condition to occur. 2. it asserts sbsy/ and its scsi id (contained in the scsi chip id (scid) register) onto the scsi bus. if the ssel/ signal is asserted by another scsi device, the SYM53C895 deasserts sbsy/, deasserts its id and sets the lost arbitration bit (bit 3) in the sstat0 register. 3. after an arbitration delay, the cpu should read the sbdl register to check if a higher priority scsi id is present. if no higher priority id bit is set, and the lost arbitration bit is not set, the SYM53C895 has won arbitration. 4. once the SYM53C895 has won arbitration, ssel/ must be asserted by using the scsi output control latch (socl) for a bus clear plus a bus settle delay (1.2 m s) before a low-level selection can be performed. 76 5 43210 arb1[1:0] start watn epc r aap trg 11000x00 arb1 arb0 arbitration mode 0 0 simple arbitration 0 1 reserved 1 0 reserved 1 1 full arbitration, selection/reselection
5-18 registers full arbitration, selection/reselection 1. the SYM53C895 waits for a bus free condition. 2. it asserts sbsy/ and its scsi id (the highest priority id stored in the scid register) onto the scsi bus. 3. if the ssel/ signal is asserted by another scsi device or if the SYM53C895 detects a higher priority id, the SYM53C895 deasserts sbsy, deasserts its id, and waits until the next bus free state to try arbitration again. 4. the SYM53C895 repeats arbitration until it wins control of the scsi bus. when it has won, the won arbitration bit is set in the sstat0 register, bit 2. 5. the SYM53C895 performs selection by asserting the following onto the scsi bus: ssel/, the target id (stored in the sdid register), and the SYM53C895 id (stored in the scsi chip id (scid) register). 6. after a selection is complete, the function complete bit is set in the sist0 register, bit 6. 7. if a selection timeout occurs, the selection timeout bit is set in the sist1 register, bit 2. start start sequence 5 when this bit is set, the SYM53C895 starts the arbitration sequence indicated by the arbitration mode bits. the start sequence bit is accessed directly in low-level mode. during scsi scripts operations, the scripts processor controls this bit. an arbitration sequence should not be started if the connected (con) bit in the scsi control one (scntl1) register, bit 4, indicates that the SYM53C895 is already connected to the scsi bus. this bit is automatically cleared when the arbitration sequence is complete. if a sequence is aborted, bit 4 in the scntl1 register should be checked to verify that the SYM53C895 did not connect to the scsi bus. watn select with satn/ on a start sequence 4 when this bit is set and the SYM53C895 is in initiator mode, the satn/ signal is asserted during SYM53C895 selection of a scsi target device. this is to inform the target that the SYM53C895 has a message to send. if a
scsi registers 5-19 selection timeout occurs while attempting to select a target device, satn/ is deasserted at the same time ssel/ is deasserted. when this bit is cleared, the satn/ signal is not asserted during selection. when executing scsi scripts, this bit is controlled by the scripts processor, but it may be set manually in low-level mode. epc enable parity checking 3 when this bit is set, the scsi data bus is checked for odd parity when data is received from the scsi bus in either initiator or target mode. parity is also checked as data goes from the scsi fifo to the dma fifo. if a parity error is detected, bit 0 of the scsi interrupt status zero (sist0) register is set and an interrupt may be generated. if the SYM53C895 is operating in initiator mode and a parity error is detected, satn/ can optionally be asserted, but the transfer continues until the target changes phase. when this bit is cleared, parity errors are not reported. r reserved 2 aap assert satn/ on parity error 1 when this bit is set, the SYM53C895 automatically asserts the satn/ signal upon detection of a parity error. satn/ is only asserted in initiator mode. the satn/ signal is asserted before deasserting sack/ during the byte transfer with the parity error. the enable parity checking bit must also be set for the SYM53C895 to assert satn/ in this manner. a parity error is detected on data received from the scsi bus. if the assert satn/ on parity error bit is cleared or the enable parity checking bit is cleared, satn/ is not automatically asserted on the scsi bus when a parity error is received. trg target mode 0 this bit determines the default operating mode of the SYM53C895. the user must manually set target or initiator mode. this can be done using the scripts language (set target or clear target). when this
5-20 registers bit is set, the chip is a target device by default. when this bit is cleared, the SYM53C895 is an initiator device by default. caution: writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes. register: 0x01 scsi control one (scntl1) read/write exc extra clock cycle of data setup 7 when this bit is set, an extra clock period of data setup is added to each scsi send data transfer. the extra data setup time can provide additional system design margin, though it affects the scsi transfer rates. clearing this bit disables the extra clock cycle of data setup time. setting this bit only affects scsi send operations. adb assert scsi data bus 6 when this bit is set, the SYM53C895 drives the contents of the scsi output data latch register (sodl) onto the scsi data bus. when the SYM53C895 is an initiator, the scsi i/o signal must be inactive to assert the sodl contents onto the scsi bus. when the SYM53C895 is a target, the scsi i/o signal must be active for the sodl contents to be asserted onto the scsi bus. the contents of the sodl register can be asserted at any time, even before the SYM53C895 is connected to the scsi bus. this bit should be cleared when executing scsi scripts. it is normally used only for diagnostics testing or operation in low-level mode. dhp disable halt on parity error or atn (target only) 5 the dhp bit is only de?ned for target mode. when this bit is cleared, the SYM53C895 halts the scsi data transfer when a parity error is detected or when the satn/ signal is asserted. if satn/ or a parity error is 76543210 exc adb dhp con rst aesp iarb sst 00000000
scsi registers 5-21 received in the middle of a data transfer, the SYM53C895 may transfer up to three additional bytes before halting to synchronize between internal core cells. during synchronous operation, the SYM53C895 transfers data until there are no outstanding synchronous offsets. if the SYM53C895 is receiving data, any data residing in the dma fifo is sent to memory before halting. when this bit is set, the SYM53C895 does not halt the scsi transfer when satn/ or a parity error is received. con connected 4 this bit is automatically set any time the SYM53C895 is connected to the scsi bus as an initiator or as a target. it is set after the SYM53C895 successfully completes arbitration or when it has responded to a bus initiated selection or reselection. this bit is also set after the chip wins simple arbitration when operating in low-level mode. when this bit is cleared, the SYM53C895 is not connected to the scsi bus. the cpu can force a connected or disconnected condition by setting or clearing this bit. this feature would be used primarily during loopback mode. rst assert scsi rst/ signal 3 setting this bit asserts the srst/ signal. the srst/ output remains asserted until this bit is cleared. the 25 m s minimum assertion time de?ned in the scsi speci?cation must be timed out by the controlling microprocessor or a scripts loop. aesp assert even scsi parity (force bad parity) 2 when this bit is set, the SYM53C895 asserts even parity. it forces a scsi parity error on each byte sent to the scsi bus from the SYM53C895. if parity checking is enabled, then the SYM53C895 checks data received for odd parity. this bit is used for diagnostic testing and should be clear for normal operation. it can be used to generate parity errors to test error handling functions. iarb immediate arbitration 1 setting this bit causes the scsi core to immediately begin arbitration once a bus free phase is detected following an expected scsi disconnect. this bit is useful
5-22 registers for multithreaded applications. the arb[1:0] bits in scsi control zero (scntl0) should be set for full arbitration and selection before setting this bit. arbitration is retried until won. at that point, the SYM53C895 holds sbsy and ssel asserted, and waits for a select or reselect sequence to be requested. the immediate arbitration bit is reset automatically when the selection or reselection sequence is completed, or times out. an unexpected disconnect condition clears iarb without attempting arbitration. see the scsi disconnect unexpected bit (scntl2, bit 7) for more information on expected versus unexpected disconnects. an immediate arbitration sequence can be aborted. first, the abort bit in the interrupt status (istat) register should be set. then one of two things will eventually happen: the won arbitration bit (sstat0 bit 2) is set. in this case, the immediate arbitration bit needs to be reset. this completes the abort sequence and disconnects the SYM53C895 from the scsi bus. if it is not acceptable to go to bus free phase immediately following the arbitration phase, a low-level selection may be performed instead. the abort completes because the SYM53C895 loses arbitration. this can be detected by the immediate arbitration bit being cleared. the lost arbitration bit (sstat0 bit 3) should not be used to detect this condition. no further action needs to be taken in this case. sst start scsi transfer 0 this bit is automatically set during scripts execution and should not be used. it causes the scsi core to begin a scsi transfer and includes sreq/sack handshaking. the determination of whether the transfer is a send or receive is made according to the value written to the i/o bit in the scsi output control latch (socl) register. this bit is self-clearing. it should not be set for low-level operation.
scsi registers 5-23 caution: writing to this register while not connected may cause the loss of a selection/reselection by clearing the connected bit. register: 0x02 scsi control two (scntl2) read/write sdu scsi disconnect unexpected 7 this bit is valid in initiator mode only. when this bit is set, the scsi core is not expecting the scsi bus to enter the bus free phase. if it does, an unexpected disconnect error is generated (see the unexpected disconnect bit in the sist0 register, bit 2). during normal scripts mode operation, this bit is set automatically whenever the scsi core is reselected, or successfully selects another scsi device. the sdu bit should be reset with a register write (move 0x00 to scntl2) before the scsi core expects a disconnect to occur. this occurs normally prior to sending an abort, abort tag, bus device reset, clear queue or release recovery message, or before deasserting sack/ after receiving a disconnect command or command complete message. chm chained mode 6 this bit determines whether or not the scsi core is programmed for chained scsi mode. this bit is automatically set by the chained block move (chmov) scripts instruction and is automatically cleared by the block move scripts instruction (move). chained mode primarily transfers consecutive wide data blocks. using chained mode facilitates partial receive transfers and allows correct partial send behavior. when this bit is set and a data transfer ends on an odd byte boundary, the SYM53C895 stores the last byte in the scsi wide residue data register during a receive operation, or in the scsi output data latch (sodl) 76 5 4 3210 sdu chm slpmd slphben wss vue0 vue1 wsr 00 0 0 0000
5-24 registers register during a send operation. this byte is combined with the ?rst byte from the subsequent transfer so that a wide transfer can be completed. for more information, see the chained mode section in chapter 2, functional description. slpmd slpar mode bit 5 if this bit is clear, the scsi longitudinal parity (slpar) register functions like the sym53c825. if this bit is set, the slpar register re?ects the high or low byte of the slpar word, depending on the state of scntl2 bit 4. it also allows a seed value to be written to the slpar register. slphben slpar high byte enable 4 if this bit is clear, the low byte of the slpar word is accessible through the slpar register. if this bit is set, the high byte of the slpar word is present in the slpar register. wss wide scsi send 3 when read, this bit returns the value of the wide scsi send (wss) ?ag. asserting this bit clears the wss ?ag. this clearing function is self-clearing. when the wss ?ag is high following a wide scsi send operation, the scsi core is holding a byte of chain data in the scsi output data latch (sodl) register. this data becomes the ?rst low-order byte sent when married with a high-order byte during a subsequent data send transfer. performing a scsi receive operation clears this bit. also, performing any non-wide transfer clears this bit. vue0 vendor unique enhancements bit 0 2 this bit is a read only value indicating whether the group code ?eld in the scsi instruction is standard or vendor unique. if reset, the bit indicates standard group codes. if set, the bit indicates vendor unique group codes. the value in this bit is reloaded at the beginning of all asynchronous target receives. the default for this bit is reset. vue1 vendor unique enhancements bit 1 1 this bit disables the automatic byte count reload during block move instructions in the command phase. if this bit
scsi registers 5-25 is reset, the device reloads the block move byte count when the ?rst byte received is one of the standard group codes. if this bit is set, the device does not reload the block move byte count, regardless of the group code. wsr wide scsi receive 0 when read, this bit returns the value of the wide scsi receive (wsr) ?ag. setting this bit clears the wsr ?ag. this clearing function is self-clearing. the wsr ?ag indicates that the scsi core received data from the scsi bus, detected a possible partial transfer at the end of a chained or nonchained block move command, and temporarily stores the high-order byte in the swide register rather than passing the byte out the dma channel. the hardware uses the wsr status ?ag to determine what behavior must occur at the start of the next data receive transfer. when the ?ag is set, the stored data in swide may be residue data, valid data for a subsequent data transfer, or overrun data. the byte may be read as normal data by starting a data receive transfer. performing a scsi send operation clears this bit. also, performing any nonwide transfer clears this bit. register: 0x03 scsi contr0l three (scntl3) read/write ultra ultra enable 7 setting this bit enables ultra scsi or ultra2 scsi synchronous transfer rates. the default value of this bit is 0. this bit should remain cleared if the SYM53C895 is not operating in ultra scsi mode or faster. set this bit to achieve ultra scsi transfer rates in legacy systems that use an 80 mhz clock. 7 6 43210 ultra scf[2:0] ews ccf[2:0] 0 0000000
5-26 registers when this bit is set, the signal ?ltering period for sreq/ and sack/ automatically changes to 8 ns for ultra2 scsi or 15 ns for ultra scsi, regardless of the value of the extend req/ack filtering bit in the stest2 register. scf[2:0] synchronous clock conversion factor [6:4] these bits select the factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. the bits are encoded as per table 5.3 . for synchronous receive, the output of this divider is always divided by 4 and that value determines the transfer rate. for example, if sclk is 160 mhz, and the scf value is set to divide by one, then the maximum synchronous receive rate is 40 mhz ( (160/1)/4 = 40) . for synchronous send, the output of this divider gets divided by the transfer period (xferp) bits in the scsi transfer (sxfer) register, and that value determines the transfer rate. for valid combinations of the scf and xferp, see table 5.5 and table 5.6 . for additional information on how the synchronous transfer rate is determined, refer to chapter 2, "functional description" . ews enable wide scsi 3 when this bit is cleared, all information transfer phases are assumed to be eight bits, and transmitted on sd[7:0]/, sdp0/. when this bit is asserted, data transfers are done 16 bits at a time, with the least signi?cant byte table 5.3 synchronous clock conversion factor scf2 scf1 scf0 factor frequency 0 0 0 sclk/3 0 0 1 sclk/1 0 1 0 sclk/1.5 0 1 1 sclk/2 1 0 0 sclk/3 1 0 1 sclk/4 1 1 0 sclk/6 1 1 1 sclk/8
scsi registers 5-27 on sd[7:0]/, sdp/ and the most signi?cant byte on sd[15:8]/, sdp1/. command, status, and message phases are not affected by this bit. clearing this bit also clears the wide scsi receive bit in the scsi control two (scntl2) register, which indicates the presence of a valid data byte in the scsi wide residue (swide) register. ccf[2:0] clock conversion factor [2:0] these bits select the frequency of the sclk for asynchronous scsi operations. the bits are encoded as per table 5.4 . for additional information on how the synchronous transfer rate is determined, refer to chapter 2, "functional description" . table 5.4 asynchronous clock conversion factor ccf2 ccf1 ccf0 scsi clock (mhz) 0 0 0 50.01C75 0 0 1 16.67C25 0 1 0 25.01C37.5 0 1 1 37.51C50 1 0 0 50.01C75 1 0 1 75.01C80.00 1 1 0 120 (not normally used) 1 1 1 160 (with clock quadrupler and 40 mhz clock)
5-28 registers register: 0x04 scsi chip id (scid) read/write r reserved 7 rre enable response to reselection 6 when this bit is set, the SYM53C895 is enabled to respond to bus-initiated reselection at the chip id in the response id zero (respid0) and response id one (respid1) registers. note that the SYM53C895 does not automatically recon?gure itself to initiator mode as a result of being reselected. sre enable response to selection 5 when this bit is set, the SYM53C895 is able to respond to bus-initiated selection at the chip id in the respid0 and respid1 registers. note that the SYM53C895 does not automatically recon?gure itself to target mode as a result of being selected. r reserved 4 enc encoded chip scsi id [3:0] these bits stores the SYM53C895 encoded scsi id. this is the id that the chip asserts when arbitrating for the scsi bus. the ids that the SYM53C895 responds to when being selected or reselected are con?gured in the respid0 and respid1 registers. the priority of the 16 possible ids, in descending order is: 7 6543210 r rre sre r enc[3:0] x 00x0000 highest lowest 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
scsi registers 5-29 register: 0x05 scsi transfer (sxfer) read/write when using table indirect i/o commands, bits [7:0] of this register are loaded from the i/o data structure. for additional information on how the synchronous transfer rate is determined, refer to chapter 2, "functional description" . tp[2:0] scsi synchronous transfer period [7:5] these bits determine the scsi synchronous transfer period (xferp) used by the SYM53C895 when sending synchronous scsi data in either initiator or target mode. these bits control the programmable dividers in the chip. for ultra scsi transfers, the ideal transfer period is 4, and 5 is acceptable. setting the transfer period to a value greater than 5 is not recommended. use this formula to calculate the synchronous send and receive rates. table 5.5 and table 5.6 show examples of possible bit combinations. 754 0 tp[2:0] mo[4:0] 00000000 tp2 tp1 tp0 xferp 0004 0015 0106 0117 1008 1019 11010 11111
5-30 registers formula: synchronous send rate = (sclk/scf) / xferp synchronous receive rate = (sclk/scf) / 4 key: sclk = scsi clock cf = synchronous clock conversion factor, scntl3 bits [6:4] xferp = transfer period, sxfer register bits [7:5] table 5.5 examples of synchronous transfer periods and rates for scsi-1 sclk (mhz) scf (scntl3 bits [6:4]) xferp (sxfer bits [7:5]) sync send rate (mbytes/s) sync send period (ns) sync receive rate (mbytes/s) synch receive period (ns) 80 ? 4 4 5 200 5 200 80 ? 4 5 4 250 5 200 66.67 ? 3 4 5.55 180 5.55 180 66.67 ? 3 5 4.44 225 5.55 180 50 ? 2 4 6.25 160 6.25 160 50 ? 2 5 5 200 6.25 160 40 ? 2 4 5 200 5 200 37.50 ? 1.5 4 6.25 160 6.25 160 33.33 ? 1.5 4 5.55 180 5.55 180 25 ? 1 4 6.25 160 6.25 160 20 ? 1 4 5 200 5 200 16.67 ? 1 4 4.17 240 4.17 240
scsi registers 5-31 mo[4:0] max scsi synchronous offset [4:0] these bits describe the maximum scsi synchronous offset used by the SYM53C895 when transferring synchronous scsi data in either initiator or target mode. table 5.7 describes the possible combinations and their relationship to the synchronous data offset used by the SYM53C895. these bits determine the SYM53C895 method of transfer for data in and data out phases only; all other information transfers occur asynchronously. table 5.6 example synchronous transfer periods and rates for fast scsi, ultra scsi, and ultra2 scsi sclk (mhz) scf (scntl3 bits [6:4]) xferp (sxfer bits [7:5]) sync send rate (mbytes/s) sync send period (ns) sync receive rate (mbytes/s) synch receive period (ns) 160 ? 1 4 40 25 40 25 80 ? 1 4 20 50 20 50 80 ? 2 4 10 100 10 100 66.67 ? 1.5 4 11.11 90 11.11 90 66.67 ? 1 5 8.88 112.5 11.11 90 50 ? 1 4 12.5 80 12.5 80 50 ? 1 5 10 100 12.5 80 40 ? 1 4 10 100 10 100 37.50 ? 1 4 9.375 106.67 9.375 106.67 33.33 ? 1 4 8.33 120 8.33 120 25 ? 1 4 6.25 160 6.25 160 20 ? 1 4 5 200 5 200 16.67 ? 1 4 4.17 240 4.17 240 table 5.7 maximum synchronous offset mo4 mo3 mo2 mo1 mo0 synchronous offset 0 0 0 0 0 0-asynchronous 00001 1 00010 2
5-32 registers 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 10001 17 10010 18 10011 19 10100 20 10101 21 10110 22 10111 23 11000 24 11001 25 11010 26 11011 27 11100 28 11101 29 11110 30 11111 31 table 5.7 maximum synchronous offset (cont.) mo4 mo3 mo2 mo1 mo0 synchronous offset
scsi registers 5-33 register: 0x06 scsi destination id (sdid) read/write r reserved [7:4] enc encoded scsi destination id [3:0] writing these bits sets the scsi id of the intended initiator or target during scsi reselection or selection phases. when executing scripts, the scripts processor writes the destination scsi id to this register. the user de?nes the scsi id in a scripts select or reselect instruction. the value written should be the binary-encoded id value. the priority of the 16 possible ids, in descending order, is: 7430 r enc[3:0] xxxx0000 highest lowest 765432101514131211098
5-34 registers register: 0x07 general purpose (gpreg) read/write r reserved [7:5] gpio[4:0] general purpose [4:0] these bits can be programmed through the gpcntl register to become inputs, outputs or to perform special functions. as an output, these pins can enable or disable external terminators. these signals can also be programmed as live inputs and sensed through a scripts register to register move instruction. gpio[3:0] default as inputs and gpio4 defaults as an output pin. gpio4 can be used to enable or disable v pp , the 12-volt power supply to the external ?ash memory. this bit powers up with the power to the external memory disabled. lsi logic symbios software uses the gpio0 pin to toggle scsi device leds, turning on the led whenever the SYM53C895 is on the scsi bus. this software drives the pin low to turn on the led or drives it high to turn off the led. lsi logic symbios software uses the gpio[1:0] pins to support serial eeprom access. when serial eeprom access is enabled, gpio1 is used as a clock and gpio0 is used as data. 754 0 r gpio[4:0] xxx0xxxx
scsi registers 5-35 register: 0x08 scsi first byte received (sfbr) read/write this register contains the ?rst byte received in any asynchronous information transfer phase. for example, when the SYM53C895 is operating in initiator mode, this register contains the ?rst byte received in the message in, status, and data in phases. when a block move instruction is executed for a particular phase, the ?rst byte received is stored in this register - even if the present phase is the same as the last phase. the ?rst byte received value for a particular input phase is not valid until after a move instruction is executed. this register is also the accumulator for register read-modify-writes with the sfbr as the destination. this allows bit testing after an operation. the sfbr is not writable through the cpu, and therefore not by a memory move. the load instruction may not be used to write to this register. however, it can be loaded by using scripts read/write operations. to load the sfbr with a byte stored in system memory, the byte must ?rst be moved to an intermediate SYM53C895 register (such as the scratch register), and then to the sfbr. this register also contains the state of the lower eight bits of the scsi data bus during the selection phase if the com bit in the dcntl register is clear. 7 0 1b[7:0] 00000000
5-36 registers register: 0x09 scsi output control latch (socl) read /write req assert scsi req/ signal 7 ack assert scsi ack/ signal 6 bsy assert scsi bsy/ signal 5 sel assert scsi sel/ signal 4 atn assert scsi atn/ signal 3 msg assert scsi msg/ signal 2 c/d assert scsi c_d/ signal 1 i/o assert scsi i_o/ signal 0 this register is used primarily for diagnostic testing or programmed i/o operation. the scripts processor controls this register when executing scsi scripts. socl should only be used when transferring data through programmed i/o. some bits are set (1) or reset (0) when executing scsi scripts. do not write to the register once the SYM53C895 starts executing normal scsi scripts. register: 0x0a scsi selector id (ssid) read only val scsi valid 7 if val is asserted, the two scsi ids were detected on the bus during a bus-initiated selection or reselection, and the encoded destination scsi id bits below are valid. if val is deasserted, only one id was present and the contents of the encoded destination id are meaningless. 76543210 req ack bsy sel atn msg c/d i/o 00000000 76543210 val r enid[3:0] 0xxx0000
scsi registers 5-37 r reserved [6:4] enid encoded scsi destination id [3:0] reading the ssid register immediately after the SYM53C895 has been selected or reselected returns the binary-encoded scsi id of the device that performed the operation. these bits are invalid for targets that are selected under the single initiator option of the scsi-1 speci?cation. this condition can be detected by examining the val bit above. register: 0x0b scsi bus control lines (sbcl) read only req sreq/ status 7 ack sack/ status 6 bsy sbsy/ status 5 sel ssel/ status 4 atn satn/ status 3 msg smsg/ status 2 c/d sc_d/ status 1 i/o si_o/ status 0 when read, this register returns the scsi control line status. a bit is set when the corresponding scsi control line is asserted. these bits are not latched. they are a true representation of what is on the scsi bus at the time the register is read. the resulting read data is synchronized before being presented to the pci bus to prevent parity errors from being passed to the system. this register can be used for diagnostics testing or operation in low-level mode. 76543210 req ack bsy sel atn msg c/d i/o xxxxxxxx
5-38 registers register: 0x0c dma status (dstat) read only reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the SYM53C895 stacks interrupts). the dip bit in the istat register is also cleared. dma interrupt conditions may be individually masked through the dien register. when performing consecutive 8-bit reads of the ds tat, sist0, and sist1 registers (in any order), insert a delay equivalent to 12 clk periods between the reads to ensure that the interrupts clear properly. refer to chapter 2, "functional description" for more information on interrupts. dfe dma fifo empty 7 this status bit is set when the dma fifo is empty. it may be used to determine if any data resides in the fifo when an error occurs and an interrupt is generated. this bit is a pure status bit and does not cause an interrupt. mdpe master data parity error 6 this bit is set when the SYM53C895 as a master detects a data parity error, or a target device signals a parity error during a data phase. the master parity error enable bit (bit 3 of ctest4) completely disables this mdpe bit 6. bf bus fault 5 this bit is set when a pci bus fault condition is detected. a pci bus fault can only occur when the SYM53C895 is bus master, and is de?ned as a cycle that ends with a bad address or target abort condition. abrt aborted 4 this bit is set when an abort condition occurs. an abort condition occurs when a software abort command is issued by setting bit 7 of the interrupt status (istat) register. 76543210 dfe mdpe bf abrt ssi sir r iid 100000x0
scsi registers 5-39 ssi single-step interrupt 3 if the single-step mode bit in the dma control (dcntl) register is set, this bit is set and an interrupt generated after successful execution of each scripts instruction. sir scripts interrupt instruction received 2 this status bit is set whenever an interrupt instruction is evaluated as true. r reserved 1 iid illegal instruction detected 0 this status bit is set any time an illegal or reserved instruction op code is detected, whether the SYM53C895 is operating in single-step mode or automatically executing scsi scripts. any of the following conditions during instruction execution also sets this bit: the SYM53C895 is executing a wait disconnect instruction and the scsi req line is asserted without a disconnect occurring. a block move instruction is executed with 0x000000 loaded into the dbc register, indicating that zero bytes are to be moved. during a transfer control instruction, the compare data (bit 18) and compare phase (bit 17) bits are set in the dma byte counter (dbc) register while the SYM53C895 is in target mode. during a transfer control instruction, the carry test bit (bit 21) is set and either the compare data (bit 18) or compare phase (bit 17) bit is set. a transfer control instruction is executed with the reserved bit 22 set. a transfer control instruction is executed with the wait for valid phase bit (bit 16) set while the chip is in target mode. a load/store instruction is issued with the memory address mapped to the operating registers of the chip, not including rom or ram. a load/store instruction is issued when the register address is not aligned with the memory address.
5-40 registers a load/store instruction is issued with bit 5 in the dcmd register clear or bits 3 or 2 set. a load/store instruction is issued when the count value in the dbc register is not set at 1 to 4. a load/store instruction attempts to cross a dword boundary. a memory move instruction is executed with one of the reserved bits in the dcmd register set. a memory move instruction is executed with the source and destination addresses not byte-aligned. register: 0x0d scsi status zero (sstat0) read only ilf sidl least signi?cant byte full 7 this bit is set when the least signi?cant byte in the scsi input data latch register (sidl) contains data. data is transferred from the scsi bus to the scsi input data latch register before being sent to the dma fifo and then to the host bus. the sidl register contains scsi data received asynchronously. synchronous data received does not ?ow through this register. orf sodr least signi?cant byte full 6 this bit is set when the least signi?cant byte in the scsi output data register (sodr, a hidden buffer register which is not accessible) contains data. the sodr register is used by the scsi logic as a second storage register when sending data synchronously. it cannot be read or written by the user. use this bit to determine how many bytes reside in the chip when an error occurs. olf sodl least signi?cant byte full 5 this bit is set when the least signi?cant byte in the scsi output data latch (sodl) contains data. the sodl register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from 76543210 ilf orf olf aip loa woa rst sdp0/ 00000000
scsi registers 5-41 the host bus to the sodl register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi bus. the sodr buffer register is not used for asynchronous transfers. use this bit to determine how many bytes reside in the chip when an error occurs. aip arbitration in progress 4 arbitration in progress (aip = 1) indicates that the SYM53C895 has detected a bus free condition, asserted sbsy, and asserted its scsi id onto the scsi bus. loa lost arbitration 3 when set, loa indicates that the SYM53C895 has detected a bus free condition, arbitrated for the scsi bus, and lost arbitration due to another scsi device asserting the sel/ signal. woa won arbitration 2 when set, woa indicates that the SYM53C895 has detected a bus free condition, arbitrated for the scsi bus and won arbitration. the arbitration mode selected in the scntl0 register must be full arbitration and selection for this bit to be set. rst/ scsi rst/ signal 1 this bit reports the current status of the scsi rst/ sig- nal, and the rst signal (bit 6) in the istat register. this bit is not latched and may be changing when read. sdp0/ scsi sdp0/ parity signal 0 this bit represents the active high current status of the scsi sdp0/ parity signal. this signal is not latched and may be changing as it is read.
5-42 registers register: 0x0e scsi status one (sstat1) read only ff[3:0] (fifo flags) [7:4] these four bits, along with sstat2 bit 4, de?ne the number of bytes or words that currently reside in the SYM53C895 scsi synchronous data fifo. these bits are not latched, and they change as data moves through the fifo. 7654 3 210 ff3 ff2 ff1 ff0 sdp0l msg c/d i/o 0000 x xxx ff4 (sstat2 bit 4) ff3 ff2 ff1 ff0 bytes or words in the scsi fifo 000000 000011 000102 000113 001004 001015 001106 001117 010008 010019 0101010 0101111 0110012 0110113 0111014 0111115 1000016
scsi registers 5-43 sdp0l latched scsi parity 3 this bit re?ects the scsi parity signal (sdp0/), corresponding to the data latched in the scsi input data latch register (sidl). it changes when a new byte is latched into the least signi?cant byte of the sidl register. this bit is active high, in other words, it is set when the parity signal is active. msg scsi msg/ signal 2 c/d scsi c_d/ signal 1 i/o scsi i_o/ signal 0 these scsi phase status bits are latched on the asserting edge of sreq/ when operating in either initiator or target mode. these bits are set when the corresponding signal is active. they are useful when operating in low-level mode. 1000117 1001018 1001119 1010020 1010121 1011022 1011123 1100024 1100125 1101026 1101127 1110028 1110129 1111030 1111131 ff4 (sstat2 bit 4) ff3 ff2 ff1 ff0 bytes or words in the scsi fifo
5-44 registers register: 0x0f scsi status two (sstat2) read only lf1 sidl most signi?cant byte full 7 this bit is set when the most signi?cant byte in the scsi input data latch register (sidl) contains data. data is transferred from the scsi bus to the scsi input data latch register before being sent to the dma fifo and then to the host bus. the sidl register contains scsi data received asynchronously. synchronous data received does not ?ow through this register. orf1 sodr most signi?cant byte full 6 this bit is set when the most signi?cant byte in the scsi output data register (sodr, a hidden buffer register which is not accessible) contains data. the sodr register is used by the scsi logic as a second storage register when sending data synchronously. it is not accessible to the user. use this bit to determine how many bytes reside in the chip when an error occurs. olf1 sodl most signi?cant byte full 5 this bit is set when the most signi?cant byte in the scsi output data latch (sodl) contains data. the sodl register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi bus. the sodr buffer register is not used for asynchronous transfers. use this bit to determine how many bytes reside in the chip when an error occurs. 76543210 ilf1 orf1 olf1 ff4 spl1 dm ldsc sdp1 0000xx1x
scsi registers 5-45 ff4 fifo flags bit 4 4 this is the most signi?cant bit in the scsi fifo flags ?eld, with the reset of the bits in sstat1. for a complete description of this ?eld, see the de?nition for sstat1 bits [7:4]. spl1 latched scsi parity for sd[15:8] 3 this active high bit re?ects the scsi odd parity signal corresponding to the data latched into the most signi?cant byte in the sidl register. dm diffsens mismatch 2 this bit is set when the diffsens pin detects a single- ended or low voltage differential scsi operating voltage level while the SYM53C895 is operating in high-power differential mode (by setting the dif bit in the stest2 register). if this bit is reset, the diffsens value matches the dif bit setting. ldsc last disconnect 1 this status bit is used in conjunction with the connected (con) bit in scntl1 and allows the user to detect the case in which a target device disconnects, and then another scsi device selects or reselects, the SYM53C895. if the connected bit is asserted and the ldsc bit is asserted, a disconnect has occurred. this bit is set when the connected bit in scntl1 is cleared. this bit is cleared when a block move instruction is executed while the connected bit in scntl1 is set. sdp1 scsi sdp1 signal 0 this bit represents the active-high current state of the scsi sdp1 parity signal. it is unlatched and may be changing as it is read.
5-46 registers register: 0x10C0x13 data structure address (dsa) read/write this 32-bit register contains the base address used for all table indirect calculations. the dsa register is usually loaded prior to starting an i/o, but it is possible for a scripts memory move to load the dsa during the i/o. during any memory to memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. register: 0x14 interrupt status (istat) read/write this is the only register that can be accessed by the host cpu while the SYM53C895 is executing scripts (without interfering in the operation of the SYM53C895). it may be used to poll for interrupts if hardware interrupts are disabled. if there are stacked interrupts pending, read this register after servicing an interrupt to check for stacked interrupts. for more information on interrupt handling refer to chapter 2, "functional description" . abrt abort operation 7 setting this bit aborts the current operation being executed by the SYM53C895. if this bit is set and an interrupt is received, clear this bit before reading the dma status (dstat) register to prevent further aborted interrupts from being generated. the sequence to abort any operation is: 1. set this bit. 2. wait for an interrupt. 3. read the istat register. 76543210 abrt srst sigp sem con intf sip dip 00000000
scsi registers 5-47 4. if the scsi interrupt pending bit is set, then read the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) register to determine the cause of the scsi interrupt and go back to step 2. 5. if the scsi interrupt pending bit is clear, and the dma interrupt pending bit is set, then write 0x00 value to this register. 6. read the dma status (dstat) register to verify the aborted interrupt and to see if any other interrupting conditions have occurred. srst software reset 6 setting this bit resets the SYM53C895. all operating registers are cleared to their respective default values and all scsi signals are deasserted. setting this bit does not cause the scsi rst/ signal to be asserted. this reset does not clear the 53c700 id mode bit or any of the pci con?guration registers. this bit is not self- clearing; it must be cleared to clear the reset condition (a hardware reset will also clear this bit). sigp signal process 5 sigp is a r/w bit that is writable at any time, and polled and reset using chip test two (ctest2). the sigp bit can be used in various ways to pass a ?ag to or from a running scripts instruction. the only scripts instruction directly affected by the sigp bit is wait for selection/reselection. setting this bit causes that instruction to jump to the alternate address immediately. the instructions at the alternate jump address should check the status of sigp to determine the cause of the jump. the sigp bit may be used at any time and is not restricted to the wait for selection/reselection condition. sem semaphore 4 this bit can be set by the scripts processor using a scripts register write instruction. the bit may also be set by an external processor while the SYM53C895 is executing a scripts operation. this bit enables the SYM53C895 to notify an external processor of a prede?ned condition while scripts are running. the
5-48 registers external processor may also notify the SYM53C895 of a prede?ned condition, and the scripts processor may take action while scripts are executing. con connected 3 this bit is automatically set any time the SYM53C895 is connected to the scsi bus as an initiator or as a target. it is set after successfully completing selection or when the SYM53C895 has responded to a bus-initiated selection or reselection. it is also set after the SYM53C895 wins arbitration when operating in low-level mode. when this bit is clear, the SYM53C895 is not connected to the scsi bus. intf interrupt on the fly 2 this bit is asserted by an intfly instruction during scripts execution. scripts programs do not halt when the interrupt occurs. this bit can be used to notify a service routine, running on the main processor while the scripts processor is still executing a scripts program. if this bit is set, when the interrupt status (istat) register is read it does not automatically clear. to clear this bit, it must be written to a one. the reset operation is self-clearing. if the intf bit is set but sip or dip is not set, do not attempt to read the other chip status registers. an interrupt-on-the-?y interrupt must be cleared before servicing any other interrupts indicated by sip or dip. this bit must be written to one in order to clear it after it has been set. sip scsi interrupt pending 1 this status bit is set when an interrupt condition is detected in the scsi portion of the SYM53C895. a scsi interrupt can occur under these conditions: a phase mismatch (initiator mode) or satn/ becomes active (target mode) an arbitration sequence completes a selection or reselection timeout occurs the SYM53C895 was selected the SYM53C895 was reselected
scsi registers 5-49 a scsi gross error occurs an unexpected disconnect occurs a scsi reset occurs a parity error is detected the handshake to handshake timer is expired the general purpose timer is expired a scsi bus mode change is detected to determine exactly which condition(s) caused the interrupt, read the sist0 and sist1 registers. dip dma interrupt pending 0 this status bit is set when an interrupt condition is detected in the dma portion of the SYM53C895. a dma interrupt can occur under these conditions: a pci parity error is detected a bus fault is detected an abort condition is detected a scripts instruction is executed in single-step mode a scripts interrupt instruction is executed an illegal instruction is detected. to determine exactly which condition(s) caused the interrupt, read the dstat register. register: 0x18 chip test zero (ctest0) read/write this was a general purpose read/write register in previous sym53c8xx family chips. although it is still a read/write register, lsi logic reserves the right to use these bits for future sym53c8xx family enhancements.
5-50 registers register: 0x19 chip test one (ctest1) read only fmt[3:0] byte empty in dma fifo [7:4] these bits identify the bottom bytes in the dma fifo that are empty. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is empty, then fmt3 is set. since the fmt ?ags indicate the status of bytes at the bottom of the fifo, if all fmt bits are set, the dma fifo is empty. ffl[3:0] byte full in dma fifo [3:0] these status bits identify the top bytes in the dma fifo that are full. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is full then ffl3 is set. since the ffl ?ags indicate the status of bytes at the top of the fifo, if all ffl bits are set, the dma fifo is full. register: 0x1a chip test two (ctest2) read/write ddir data transfer direction (read only) 7 this status bit indicates which direction data is being transferred. when this bit is set, the data is transferred from the scsi bus to the host bus. when this bit is clear, the data is transferred from the host bus to the scsi bus. sigp signal process (read only) 6 this bit is a copy of the sigp bit in the istat register (bit 5). use the sigp bit to signal a running scripts instruction. when this register is read, the sigp bit in the istat register is cleared. 76543210 fmt3 fmt2 fmt1 fmt0 ffl3 ffl2 ffl1 ffl0 11110000 76543210 ddir sigp cio cm srtch teop dreq dack 00xx 0 001
scsi registers 5-51 cio con?gured as i/o (read only) 5 this bit is de?ned as the con?guration i/o enable status bit. this read-only bit indicates if the chip is currently enabled as i/o space. note: both bits 4 and 5 may be set if the chip is dual mapped. cm con?gured as memory (read only) 4 this bit is de?ned as the con?guration memory enable status bit. this read-only bit indicates if the chip is cur- rently enabled as memory space. note: both bits 4 and 5 may be set if the chip is dual-mapped. bsrtch scratcha/b operation 33 this bit controls the operation of the scratcha and scratchb registers. when it is set, scratchb contains the ram base address value from the pci con?guration ram base address register. this is the base address for the 4 kbytes internal ram. in addition, the scratcha register displays the memory-mapped based address of the chip operating registers. when this bit is clear, the scratcha and scratchb registers return to normal operation. bit 3 is the only writable bit in this register. all other bits are read only. when modifying this register, all other bits must be written to zero. do not execute a read-modify- write to this register. teop scsi true end of process (read only) 2 this bit indicates the status of the SYM53C895 internal teop signal. the teop signal acknowledges the completion of a transfer through the scsi portion of the SYM53C895. when this bit is set, teop is active. when this bit is clear, teop is inactive. dreq data request status (read only) 1 this bit indicates the status of the SYM53C895 internal data request signal (dreq). when this bit is set, dreq is active. when this bit is clear, dreq is inactive. dack data acknowledge status (read only) 0 this bit indicates the status of the SYM53C895 internal data acknowledge signal (dack/). when this bit is set, dack/ is inactive. when this bit is clear, dack/ is active.
5-52 registers register: 0x1b chip test three (ctest3) read/write v[3:0] chip revision level [7:4] these bits identify the chip revision level for software purposes. the value should be the same as the lower nibble of the pci revision id register, at address 0x08 in con?guration space. flf flush dma fifo 3 when this bit is set, data residing in the dma fifo is transferred to memory, starting at the address in the dnad register. the internal dmawr signal, controlled by the ctest5 register, determines the direction of the transfer. this bit is not self clearing; once the SYM53C895 has successfully transferred the data, this bit should be reset. polling of fifo ?ags is allowed during ?ush operations. clf clear dma fifo 2 when this bit is set, all data pointers for the dma fifo are cleared. any data in the fifo is lost. this bit automatically resets after the SYM53C895 has success- fully cleared the appropriate fifo pointers and registers. this bit does not clear the data visible at the bottom of the fifo. fm fetch pin mode 1 when set, this bit causes the fetch/ pin to deassert during indirect and table indirect read operations. fetch/ is only active during the op code portion of an instruction fetch. this allows scripts to be stored in a prom while data tables are stored in ram. if this bit is not set, fetch/ is asserted for all bus cycles during instruction fetches. 76543210 v3 v2 v1 v0 flf clf fm wrie xxxx0000
scsi registers 5-53 wrie write and invalidate enable 0 this bit, when set, causes memory write and invalidate commands to be issued on the pci bus after certain conditions have been met. these conditions are described in detail in chapter 3, "pci functional description" . register: 0x1cC0x1f temporary (temp) read/write this 32-bit register stores the return instruction address pointer from the call instruction. the address pointer stored in this register is loaded into the dsp register when a return instruction is executed. this address points to the next instruction to be executed. do not write to this register while the SYM53C895 is executing scripts. during any memory to memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. register: 0x20 (a0) dma fifo (dfifo) read only bo[7:0] byte offset counter [7:0] these bits, along with bits [1:0] in the ctest5 register, indicate the amount of data transferred between the scsi core and the dma core. it may be used to determine the number of bytes in the dma fifo when an interrupt occurs. these bits are unstable while data is being transferred between the two cores. once the chip has stopped transferring data, these bits are stable. since the dfifo register counts the number of bytes transferred between the dma core and the scsi core, and the dbc register counts the number of bytes 7 0 bo[7:0] x0000000
5-54 registers transferred across the host bus, the difference between these two counters represents the number of bytes remaining in the dma fifo. follow these steps to determine how many bytes are left in the dma fifo when an error occurs, regardless of the direction of the transfer: 1. if the dma fifo size is set to 112 bytes, subtract the seven least signi?cant bits of the dbc register from the 7-bit value of the dfifo register. if the dma fifo size is set to 816 bytes (using bit 5 of the ctest5 register), subtract the 10 least signi?cant bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the ctest5 register and bits [7:0] of the dma fifo register. 2. if the dma fifo size is set to 112 bytes, and the result with 0x7f for a byte count between zero and 64. if the dma fifo size is set to 816 bytes, and the result with 0x3ff for a byte count between 0 and 816. to calculate the total number of bytes in both the dma fifo and scsi logic, refer to the section on data paths in chapter two, functional description. register: 0x21 chip test four (ctest4) read/write bdis burst disable 7 when set, this bit causes the SYM53C895 to perform back to back cycles for all transfers. when reset, the SYM53C895 will perform back to back transfers for op code fetches and burst transfers for data moves. zmod high impedance mode 6 setting this bit causes the SYM53C895 to place all output and bidirectional pins into a high-impedance state. in 765432 0 bdis zmod zsd srtm mpee fbl[2:0] 00000000
scsi registers 5-55 order to read data out of the SYM53C895, this bit must be cleared. this bit is intended for board-level testing only. do not set this bit during normal system operation. zsd scsi data high impedance 5 setting this bit causes the SYM53C895 to place the scsi data bus sd[15:0] and the parity lines sdp[1:0] in a high- impedance state. in order to transfer data on the scsi bus, this bit must be cleared. srtm shadow register test mode 4 setting this bit allows access to the shadow registers used by memory to memory move operations. when this bit is set, register accesses to the temp and dsa registers are directed to the shadow copies stemp (shadow temp) and sdsa (shadow dsa). the registers are shadowed to prevent them from being over- written during a memory to memory move operation. the dsa and temp registers contain the base address used for table indirect calculations, and the address pointer for a call or return instruction. this bit is intended for manufacturing diagnostics only and should not be set during normal operations. mpee master parity error enable 3 setting this bit enables parity checking during master data phases. a parity error during a bus master read is detected by the SYM53C895. a parity error during a bus master write is detected by the target, and the SYM53C895 is informed of the error by the perr/ pin being asserted by the target. when this bit is reset, the SYM53C895 does not interrupt if a master parity error occurs. this bit is reset at power up. fbl[2:0] fifo byte control [2:0] fbl2 fbl1 fbl0 dma fifo byte lane pins 0 x x disabled n/a 1 0 0 0 d[7:0] 1 0 1 1 d[15:8] 1 1 0 2 d[23:16] 1 1 1 3 d[31:24]
5-56 registers these bits steer the contents of the ctest6 register to the appropriate byte lane of the 32-bit dma fifo. if the fbl2 bit is set, then fbl1 and fbl0 determine which of four byte lanes can be read or written. when cleared, the byte lane read or written is determined by the current contents of the dnad and dbc registers. each of the four bytes that make up the 32-bit dma fifo can be accessed by writing these bits to the proper value. for normal operation, fbl2 must equal zero. register: 0x22 chip test five (ctest5) read/write adck clock address incrementor 7 setting this bit increments the address pointer contained in the dnad register. the dnad register is incremented based on the dnad contents and the current dbc value. this bit automatically clears itself after incrementing the dnad register. bbck clock byte counter 6 setting this bit decrements the byte count contained in the 24-bit dbc register. it is decremented based on the dbc contents and the current dnad value. this bit auto- matically clears itself after decrementing the dbc regis- ter. dfs dma fifo size 5 this bit controls the size of the dma fifo. when clear, the dma fifo is 112 bytes deep. when set, the dma fifo size increases to 816 bytes. using a 112-byte fifo allows software written for other sym53c8xx family chips to properly calculate the number of bytes residing in the chip after a target disconnect. the default value of this bit is zero. 76543210 adck bbck dfs masr ddir bl2 bo[9:8] 00000xxx
scsi registers 5-57 masr master control for set or reset pulses 4 this bit controls the operation of bit 3. when this bit is set, bit 3 asserts the corresponding signals. when this bit is reset, bit 3 deasserts the corresponding signals. bits 4 and 3 should not be changed in the same write cycle. ddir dma direction 3 setting this bit either asserts or deasserts the internal dma write (dmawr) direction signal depending on the current status of the masr bit in this register. asserting the dmawr signal indicates that data is transferred from the scsi bus to the host bus. deasserting the dmawr signal transfers data from the host bus to the scsi bus. bl2 burst length bit 2 2 this bit works with bits 6 and 7 in the dmode register to determine the burst length. for complete de?nitions of this ?eld, refer to the descriptions of dmode bits 6 and 7. this bit is disabled if an 112-byte fifo is selected by clearing the dma fifo size bit. bo[9:8] dma fifo offset [1:0] these are the upper two bits of the dma fifo byte offset counter. the entire ?eld is described under the dfifo register, bits [7:0]. register: 0x23 chip test six (ctest6) read/write df[7:0] dma fifo [7:0] writing to this register writes data to the appropriate byte lane of the dma fifo as determined by the fbl bits in the ctest4 register. reading this register unloads data from the appropriate byte lane of the dma fifo as determined by the fbl bits in the ctest4 register. data written to the fifo is loaded into the top of the fifo. data read out of the fifo is taken from the bottom. to prevent dma data from being corrupted, this register should not be accessed during normal operation. this 76543210 df[7:0] 00000000
5-58 registers register should only be written when testing the dma fifo using the ctest4 register. reads or writes to this register while the test mode is not enabled will have unexpected results. register: 0x24C0x26 dma byte counter (dbc) read/write this 24-bit register determines the number of bytes to be transferred in a block move instruction. while sending data to the scsi bus, the counter is decremented as data is moved into the dma fifo from memory. while receiving data from the scsi bus, the counter is decremented as data is written to memory from the SYM53C895. the dbc counter is decremented each time that data is transferred on the pci bus. it is decremented by an amount equal to the number of bytes that were transferred. the maximum number of bytes that can be transferred in any one block move command is 16,777,215 bytes. the maximum value that can be loaded into the dbc register is 0xffffff. if the instruction is a block move and a value of 0x000000 is loaded into the dbc register, an illegal instruction interrupt occurs if the SYM53C895 is not in target mode, command phase. use the dbc register to also hold the least signi?cant 24 bits of the ?rst dword of a script fetch, and to hold the offset value during table indirect i/o scripts. for a complete description, refer to section 6.4, i/o instruction the power-up value of this register is indeterminate. register: 0x27 dma command (dcmd) read/write this 8-bit register determines the instruction for the SYM53C895 to execute. this register has a different format for each instruction. for complete descriptions, refer to section 6.4, i/o instruction .
scsi registers 5-59 register: 0x28C0x2b dma next address (dnad) read/write this 32-bit register contains the general purpose address pointer. at the start of some scripts operations, its value is copied from the dsps register. its value may not be valid except in certain abort conditions. the default value of this register is zero. this register should not be used to determine data addresses during a phase mismatch interrupt, as its value is not always correct for this use. the dbc, dfifo, and dsps registers should be used to calculate residual byte counts and addresses as described in section 2.2.1.1, data paths . register: 0x2cC0x2f dma scripts pointer (dsp) read/write to execute scsi scripts, the address of the ?rst scripts instruction must be written to this register. in normal scripts operation, once the starting address of the script is written to this register, scripts are automatically fetched and executed until an interrupt condition occurs. in single-step mode, there is a single step interrupt after each instruction is executed. the dsp register does not need to be written with the next address, but the start dma bit (bit 2, dcntl register) must be set each time the step interrupt occurs to fetch and execute the next scripts command. when writing to this register eight bits at a time, writing the upper eight bits begins execution of scsi scripts. the default value of this register is zero. register: 0x30C0x33 dma scripts pointer save (dsps) read/write this register contains the second dword of a scripts instruction. it is overwritten each time a scripts instruction is fetched. when a scripts interrupt instruction is executed, this register holds the interrupt vector. the power-up value of this register is indeterminate.
5-60 registers register: 0x34C0x37 scratch register a (scratch a) read/write this is a general purpose, user-de?nable scratch pad register. apart from cpu access, only register read/write and memory moves into the scratch register will alter its contents. the SYM53C895 cannot fetch scripts instructions from this location. when bit 3 in the ctest2 register is set, this register contains the memory-mapped base address of the operating registers. setting ctest2 bit 3 only causes the base address to appear in this register. any information that was previously in the register remains intact. any writes to this register while ctest2 bit 3 is set passes through to the actual scratcha register. the power-up value of this register is indeterminate. register: 0x38 dma mode (dmode) read/write bl[1:0] burst length [7:6] these bits control the maximum number of transfers performed per bus ownership, regardless of whether the transfers are back to back, burst, or a combination of both. the SYM53C895 asserts the bus request (req/) output when the dma fifo can accommodate a transfer of at least one burst size of data. bus request (req/) is also asserted during start-of-transfer and end-of-transfer cleanup and alignment, even though less than a full burst of transfers may be performed. the SYM53C895 inserts a fairness delay of four clks between burst-length transfers (as set in bl[1:0]) during normal operation. the fairness delay is not inserted during pci retry cycles. this gives the cpu and other bus master devices the opportunity to access the pci bus between bursts. 76543210 bl[1:0] siom diom erl ermp bof man 00000000
scsi registers 5-61 siom source i/o-memory enable 5 this bit is de?ned as an i/o memory enable bit for the source address of a memory move or block move command. if this bit is set, then the source address is in i/o space. if reset, then the source address is in memory space. this function is useful for register to memory operations using the memory move instruction when the SYM53C895 is i/o mapped. use bits 4 and 5 of the ctest2 register to determine the con?guration status of the SYM53C895. diom destination i/o-memory enable 4 this bit is de?ned as an i/o memory enable bit for the destination address of a memory move or block move command. if this bit is set, then the destination address is in i/o space. if reset, then the destination address is in memory space. this function is useful for memory to register operations using the memory move instruction when the SYM53C895 is i/o mapped. bits 4 and 5 of the ctest2 register can be used to determine the con?guration status of the SYM53C895. erl enable read line 3 this bit enables a pci read line command. if pci cache mode is enabled by setting bits in the pci cache line size register, this chip issues a read line command on bl2 (ctest5 bit 2) bl1 bl0 burst length 0 0 0 2-transfer burst 0 0 1 4-transfer burst 0 1 0 8-transfer burst 0 1 1 16-transfer burst 1 0 0 32-transfer burst 1 1 0 1 64-transfer burst 1 1 1 0 128-transfer burst 1 1 1 1 reserved 1. only valid if the fifo size is set to 816 bytes.
5-62 registers all read cycles if other conditions are met. for more information on these conditions, refer to section 3.1, pci addressing . ermp enable read multiple 2 setting this bit causes read multiple commands to be issued on the pci bus after certain conditions have been met. these conditions are described in section 3.1, pci addressing . bof burst op code fetch enable 1 setting this bit causes the SYM53C895 to fetch instructions in burst mode. speci?cally, the chip bursts in the ?rst two dwords of all instructions using a single bus ownership. if the instruction is a memory to memory move type, the third dword is accessed in a subsequent bus ownership. if the instruction is an indirect type, the additional dword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move type, the chip accesses the remaining two dwords in a subsequent bus ownership, thereby fetching the four dwords required in two bursts of two dwords each. this bit has no effect if scripts instruction prefetching is enabled. man manual start mode 0 setting this bit prevents the SYM53C895 from automatically fetching and executing scsi scripts when the dsp register is written. when this bit is set, the start dma bit in the dcntl register must be set to begin scripts execution. clearing this bit causes the SYM53C895 to automatically begin fetching and executing scsi scripts when the dsp register is written. this bit normally is not used for scsi scripts operations.
scsi registers 5-63 register: 0x39 dma interrupt enable (dien) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the dstat register. an interrupt is masked by clearing the appropriate mask bit. masking an interrupt prevents irq/ from being asserted for the corresponding interrupt, but the status bit is still set in the dstat register. masking an interrupt does not prevent the istat dip from being set. all dma interrupts are considered fatal, therefore scripts stops running when this condition occurs, whether or not the interrupt is masked. setting a mask bit enables the assertion of irq/ for the corresponding interrupt. (a masked nonfatal interrupt does not prevent unmasked or fatal interrupts from getting through; interrupt stacking begins when either the istat sip or dip bit is set.) the SYM53C895 irq/ output is latched; once asserted, it remains asserted until the interrupt is cleared by reading the appropriate status register. masking an interrupt after the irq/ output is asserted does not cause irq/ to be deasserted. for more information on interrupts, refer to section chapter 2, functional description . r reserved 7 mdpe master data parity error 6 bf bus fault 5 abrt aborted 4 ssi single-step interrupt 3 sir scripts interrupt instruction received 2 76543210 r mdpe bf abrt ssi sir r iid x00000x0
5-64 registers r reserved 1 iid illegal instruction detected 0 register: 0x3a scratch byte register (sbr) read/write this is a general purpose register. apart from cpu access, only register read/write and memory moves into this register alters its contents. the default value of this register is zero. this register was called the dma watchdog timer on previous sym53c8xx family products. register: 0x3b dma control (dcntl) read/write clse cache line size enable 7 setting this bit enables the SYM53C895 to sense and react to cache line boundaries set up by the dmode or pci cache line size register, whichever contains the smaller value. clearing this bit disables the cache line size logic and the SYM53C895 monitors the cache line size by using the dmode register. pff prefetch flush 6 setting this bit causes the pre-fetch unit to ?ush its contents. the bit resets after the ?ush is complete. pfen prefetch enable 5 setting this bit enables the pre-fetch unit if the burst size is equal to or greater than four. for more information on scripts instruction prefetching, refer to chapter 2 "functional description." ssm single-step mode 4 setting this bit causes the SYM53C895 to stop after executing each scripts instruction, and generate a single step interrupt. when this bit is clear the SYM53C895 does not stop after each instruction; instead 76543210 clse pff pfen ssm irqm std irqd com 00000000
scsi registers 5-65 it continues fetching and executing instructions until an interrupt condition occurs. for normal scsi scripts operation, this bit should be clear. to restart the SYM53C895 after it generates a scripts step interrupt, the istat and dstat registers should be read to recognize and clear the interrupt and then the start dma bit in this register should be set. irqm irq mode 3 when set, this bit enables a totem pole driver for the irq pin. when reset, this bit enables an open drain driver for the irq pin with a internal weak pull-up. this bit is reset at power up. this bit should remain clear to retain full pci compliance. std start dma operation 2 the SYM53C895 fetches a scsi scripts instruction from the address contained in the dsp register when this bit is set. this bit is required if the SYM53C895 is in one of the following modes: manual start mode C bit 0 in the dmode register is set. single-step mode C bit 4 in the dcntl register is set. when the SYM53C895 is executing scripts in manual start mode, the start dma bit needs to be set to start instruction fetches, but does not need to be set again until an interrupt occurs. when the SYM53C895 is in single-step mode, the start dma bit needs to be set to restart execution of scripts after a single-step interrupt. irqd irq disable 1 setting this bit disables the irq pin and clearing this bit enables normal operation. as with any other register other than is tat, this register cannot be accessed except by a scripts instruction during scripts execution. for more information on the use of this bit in interrupt handling, refer to chapter 2, "functional desription." com sym53c700 compatibility 0 when this bit is clear, the SYM53C895 behaves in a manner compatible with the sym53c700 in that selection/reselection ids are stored in both the ssid and sfbr registers.
5-66 registers when this bit is set, the id is stored only in the ssid register, protecting the sfbr from being overwritten if a selection/reselection occurs during a dma register to register operation. this bit is not affected by a software reset. register: 0x3cC0x3f adder sum output (adder) read only this register contains the output of the internal adder, and is used primarily for test purposes. the power-up value for this register is indeterminate. register: 0x40 scsi interrupt enable zero (sien0) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the sist0 register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts, refer to chapter 2, functional description. m/a scsi phase mismatch - initiator mode; scsi atn condition - target mode setting this bit allows the SYM53C895 to generate an interrupt when a phase mismatch or atn condition occurs. cmp function complete 6 setting this bit allows the SYM53C895 to generate an interrupt when a full arbitration and selection sequence has completed. sel selected 5 setting this bit allows the SYM53C895 to generate an interrupt when the SYM53C895 has been selected by a scsi target device. 76543210 m/a cmp sel rsl sge udc rst par 00000000
scsi registers 5-67 rsl reselected 4 setting this bit allows the SYM53C895 to generate an interrupt when the SYM53C895 has been reselected by a scsi initiator device. sge scsi gross error 3 setting this bit allows the SYM53C895 to generate an interrupt when a scsi gross error occurs. the following conditions are considered scsi gross errors: data under?ow - the scsi fifo was read when no data was present. data over?ow - the scsi fifo was written to while full. offset under?ow - in target mode, a sack/ pulse was received before the corresponding sreq/ was sent. offset over?ow - in initiator mode, an sreq/ pulse was received which caused the maximum offset (de?ned by the mo[3:0] bits in the sxfer register) to be exceeded. in initiator mode, a phase change occurred with an outstanding sreq/sack offset. residual data in scsi fifo - a transfer other than synchronous data receive was started with data left in the scsi synchronous receive fifo. udc unexpected disconnect 2 setting this bit allows the SYM53C895 to generate an interrupt when an unexpected disconnect occurs.this condition only occurs in initiator mode. it happens when the target to which the SYM53C895 is connected disconnects from the scsi bus unexpectedly. see the scsi disconnect unexpected bit in the scntl2 register for more information on expected versus unexpected disconnects. any disconnect in low-level mode causes this condition. rst scsi reset condition 1 setting this bit allows the SYM53C895 to generate an interrupt when the srst/ signal has been asserted by the SYM53C895 or any other scsi device. this condition is edge-triggered, so multiple interrupts cannot occur because of a single srst/ pulse.
5-68 registers par scsi parity error 0 setting this bit allows the SYM53C895 to generate an interrupt when the SYM53C895 detects a parity error while receiving or sending scsi data. see the disable halt on parity error or satn/ condition bits in the scntl1 register for more information on when this condition will actually be raised. register: 0x41 scsi interrupt enable one (sien1) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the sist1 register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts, refer to chapter 2, "functional description" . r reserved [7:5] bsbmc scsi bus mode change 4 setting this bit allows the SYM53C895 to generate an interrupt when the diffsens pin detects a change in voltage level that indicates the scsi bus has changed between single-ended, lvd, or hvd modes. for example, when this bit is clear and the scsi bus changes modes, irq/ does not assert and the sip bit in the istat register is not set. however, bit 4 in the sist1 register is set. setting this bit allows the interrupt to occur. r reserved 3 sto selection or reselection timeout 2 setting this bit allows the SYM53C895 to generate an interrupt when a selection or reselection timeout occurs. see the description of the scsi timer zero (stime0) register (bits [3:0]) on page 5-76 for more information on the timeout periods. 76543210 r sbmc r sto gen hth xxx0x000
scsi registers 5-69 gen general purpose timer expired 1 setting this bit allows the SYM53C895 to generate an interrupt when the general purpose timer has expired. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register (bits [3:0]) on page 5-77 for more information on the general purpose timer. hth handshake to handshake timer expired 0 setting this bit allows the SYM53C895 to generate an interrupt when the handshake to handshake timer has expired. the time measured is the scsi request to request (target) or acknowledge to acknowledge (initiator) period. see the description of the stime0 register, bits [7:4], for more information on the handshake to handshake timer. register: 0x42 scsi interrupt status zero (sist0) read only reading the sist0 register returns the status of the various interrupt conditions, whether they are enabled in the sien0 register or not. each bit set indicates that the corresponding condition has occurred. reading the sist0 clears the interrupt status. reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the SYM53C895 stacks interrupts). scsi interrupt conditions may be individually masked through the scsi interrupt enable zero (sien0) register. when performing consecutive 8-bit reads of the ds tat, sist0, and sist1 registers (in any order), insert a delay equivalent to 12 clk periods between the reads to ensure the interrupts clear properly. also, if reading the registers when both the interrupt status (istat) sip and dip bits may not be set, the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers should be read before the dma status (dstat) register to avoid missing a scsi interrupt. for more information on interrupts, refer to chapter 2, "functional description" 76543210 m/a cmp sel rsl sge udc rst par 00000000
5-70 registers m/a initiator mode: phase mismatch; target mode: satn/ active 7 in initiator mode, this bit is set if the scsi phase asserted by the target does not match the instruction. the phase is sampled when sreq/ is asserted by the target. in target mode, this bit is set when the satn/ signal is asserted by the initiator. cmp function complete 6 this bit is set when an arbitration only or full arbitration sequence has completed. sel selected 5 this bit is set when the SYM53C895 is selected by another scsi device. the enable response to selection bit must have been set in the scsi chip id (scid) register (and the response id (respid) register must hold the chip id) for the SYM53C895 to respond to selec- tion attempts. rsl reselected 4 this bit is set when the SYM53C895 is reselected by another scsi device. the enable response to reselection bit must have been set in the scsi chip id (scid) register (and the response id (respid) register must hold the chip id) for the SYM53C895 to respond to reselection attempts. sge scsi gross error 3 this bit is set when the SYM53C895 encounters a scsi gross error condition. these conditions can result in a scsi gross error condition: data under?ow - the scsi fifo register was read when no data was present. data over?ow - too many bytes were written to the scsi fifo or the synchronous offset caused the scsi fifo to be overwritten. offset under?ow - the SYM53C895 is operating in target mode and a sack/ pulse is received when the outstanding offset is zero. offset over?ow - the other scsi device sent a sreq/ or sack/ pulse with data which exceeded the maximum synchronous offset de?ned by the sxfer register.
scsi registers 5-71 a phase change occurred with an outstanding synchronous offset when the SYM53C895 was operating as an initiator. residual data in the synchronous data fifo - a transfer other than synchronous data receive was started with data left in the synchronous data fifo. udc unexpected disconnect 2 this bit is set when the SYM53C895 is operating in initiator mode and the target device unexpectedly disconnects from the scsi bus. this bit is only valid when the SYM53C895 operates in the initiator mode. when the SYM53C895 operates in low-level mode, any disconnect causes an interrupt, even a valid scsi disconnect. this bit is also set if a selection timeout occurs. it may occur before, at the same time, or stacked after the sto interrupt, since this is not considered an expected disconnect. rst scsi reset received 1 this bit is set when the SYM53C895 detects an active srst/ signal, whether the reset was generated external to the chip or caused by the assert srst/ bit in the scntl1 register. this SYM53C895 scsi reset detection logic is edge-sensitive, so that multiple interrupts are not generated for a single assertion of the srst/ signal. par parity error 0 this bit is set when the SYM53C895 detects a parity error while receiving scsi data. the enable parity checking bit (bit 3 in the scntl0 register) must be set for this bit to become active. the SYM53C895 always generates parity when sending scsi data.
5-72 registers register: 0x43 scsi interrupt status one (sist1) read only reading the sist1 register returns the status of the various interrupt conditions, whether they are enabled in the sien1 register or not. each bit that is set indicates the corresponding condition has occurred. reading the sist1 and sist0 registers clears the interrupt condition. r reserved [7:5] sbmc scsi bus mode change 4 this bit is set when the diffsens pin detects a change in voltage level that indicates the scsi bus has switched between single-ended, lvd, or hvd modes. r reserved 3 sto selection or reselection timeout 2 the scsi device which the SYM53C895 was attempting to select or reselect did not respond within the programmed timeout period. see the description of the scsi timer zero (stime0) register (bits [3:0]) on page 5-76 for more information on the timeout timer. gen general purpose timer expired 1 this bit is set when the general purpose timer has expired. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register (bits [3:0]) on page 5-77 for more information on the general purpose timer. hth handshake to handshake timer expired 0 this bit is set when the handshake to handshake timer has expired. the time measured is the scsi request to request (target) or acknowledge to acknowledge (initiator) period. see the description of the stime0 register, bits [7:4], for more information on the handshake to handshake timer. 76543210 r sbmc r sto gen hth xxx0x000
scsi registers 5-73 register: 0x44 scsi longitudinal parity (slpar) read/write the slpar register consists of two multiplexed bytes; other register bit settings determine what is displayed at this memory location at any given time. when bit 5 in the scsi control two (scntl2) (slpmd) register is cleared, the chip xors the high and low bytes of the slpar register together to give a single-byte value which is displayed in the slpar register. if the slpmd bit is set, then the slpar register shows either the high byte or the low byte of the slpar word. the slpar high byte enable bit, scntl2 bit 4, determines which byte of the slpar register is visible on the slpar register at any given time. if this bit is cleared, the slpar register contains the low byte of the slpar word. if it is set, the slpar register contains the high byte of the slpar word. this register performs a bytewise longitudinal parity check on all scsi data received or sent through the scsi core. if one of the bytes received or sent (usually the last) is the set of correct even parity bits, slpar should go to zero (assuming it started at zero). as an example, suppose that the following three data bytes and one check byte are received from the scsi bus (all signals are shown active high): a one in any bit position of the ?nal slpar value would indicate a transmission error. the slpar register can also be used to generate the check bytes for scsi send operations. if the slpar register contains all zeros prior to sending a block move, it will contain the appropriate check byte at the end of the block move. this byte must then be sent across the scsi bus. note: writing any value to this register resets it to zero. data bytes running slpar --- 00000000 1. 11001100 11001100 (xor of word 1) 2. 01010101 10011001 (xor of word 1 and 2) 3. 00001111 10010110 (xor of word 1, 2 and 3) even parity >>>10010110 4. 10010110 00000000
5-74 registers the longitudinal parity checks are meant to provide an added measure of scsi data integrity and are entirely optional. this register does not latch scsi selection/reselection ids under any circumstances. the default value of this register is zero. register: 0x45 scsi wide residue (swide) read only after a wide scsi data receive operation, this register contains a residual data byte if the last byte received was never sent across the dma bus. it represents either the ?rst data byte of a subsequent data transfer, or it is a residue byte which should be cleared when an ignore wide residue message is received. it may also be an overrun data byte. the power-up value of this register is indeterminate. register: 0x46 memory access control (macntl) read/write typ[7:4] chip type [7:4] these bits identify the chip type for software purposes. this data manual applies to devices that have these bits set to 0xd0. bits 3 through 0 of this register determine if an external bus master access is to local or far memory. when bits 3 through 0 are set, the corresponding access is considered local and the mac/_testout pin is driven high. when these bits are clear, the corresponding access is to far memory and the mac/_testout pin is driven low. this function is enabled after a transfer control scripts instruction is executed. dwr data write 3 this bit de?nes if a data write is considered local memory access. 765432 1 0 typ[7:4] dwr drd pscpt scpts 110100 0 0
scsi registers 5-75 drd data read 2 this bit de?nes if a data read is considered local memory access. pscpt pointer scripts 1 this bit de?nes if a pointer to a scripts indirect or table indirect fetch is considered local memory access. scpts scripts 0 this bit de?nes if a scripts fetch is considered local memory access. register: 0x47 general purpose pin control (gpcntl) read/write this register determines if the pins controlled by the general purpose register (gpreg) are inputs or outputs. bits [4:0] in gpcntl correspond to bits [4:0] in the gpreg register. me master enable 7 the internal bus master signal is presented on gpio1 if this bit is set, regardless of the state of bit 1 (gpio1_en). fe fetch enable 6 the internal op code fetch signal will be presented on gpio0 if this bit is set, regardless of the state of bit 0 (gpio0_en). r reserved 5 gpio_en gpio enable [4:2] general purpose control, corresponding to bits [4:2] in the gpreg register and pins [67:65]. gpio4 powers up as a general purpose output, and gpio[3:2] power up as general purpose inputs. 76543210 me fe r gpio[4:0] 00x01111
5-76 registers gpio_en gpio enable [1:0] these bits power up set, causing the gpio1 and gpio0 pins to become inputs. resetting these bits causes gpio[1:0] to become outputs. register: 0x48 scsi timer zero (stime0) read/write hth[7:4] handshake to handshake timer period [7:4] these bits select the handshake to handshake timeout period, the maximum time between scsi handshakes (sreq/ to sreq/ in target mode, or sack/ to sack/ in initiator mode). when this timing is exceeded, an interrupt is generated and the hth bit in the sist1 register is set. table 5.8 contains timeout periods for the handshake to handshake timer, the selection/reselection timer (bits [3:0]), and the general purpose timer (stime1 bits [3:0]). for a more detailed explanation of interrupts, refer to chapter 2, "functional description" . 76543210 hth[7:4] sel[3:0] 00000000 table 5.8 timeout periods 1 hth[7:4], sel[3:0], gen[3:0] minimum timeout (40 or 160 mhz) 2 0000 disabled 0001 125 m s 0010 250 m s 0011 500 m s 0100 1 ms 0101 2 ms 0110 4 ms 0111 8 ms 1000 16 ms 1001 32 ms
scsi registers 5-77 sel[3:0] selection timeout [3:0] these bits select the scsi selection/reselection timeout period. when this timing (plus the 200 m s selection abort time) is exceeded, the sto bit in the sist1 register is set. for a more detailed explanation of interrupts, refer to chapter 2, functional description. register: 0x49 scsi timer one (stime1) read/write r reserved 7 hthba handshake to handshake timer bus activity enable 6 setting this bit causes this timer to begin testing for scsi req/ack activity as soon as sbsy/ is asserted, regardless of the agents participating in the transfer. gensf (general purpose timer scale factor) 5 setting this bit causes this timer to shift by a factor of 16. see table 5.9 for timeout periods, 50 mhz clock and table 5.10 for timeout periods, 40 mhz clock. 1010 64 ms 1011 128 ms 1100 256 ms 1101 512 ms 1110 1.024 sec 1111 2.048 sec 1. these values are correct if the ccf bits in the scntl3 register are set according to the valid combinations in the bit description. 2. a quadrupled 40 mhz clock is required for ultra2 scsi operation. table 5.8 timeout periods 1 (cont.) hth[7:4], sel[3:0], gen[3:0] minimum timeout (40 or 160 mhz) 2 7 6 5 4 3210 r hthba gensf hthsf gen[3:0] x 0 0 0 0000
5-78 registers table 5.9 timeout periods, 50 mhz clock 1 hth[7:4], sel[3:0], gen[3:0] minimum timeout (50 mhz clock) 2 gensf = 0 gensf = 1 0000 disabled disabled 0001 100 m s 1.6 ms 0010 200 m s 3.2 ms 0011 400 m s 6.4 ms 0100 800 m s 12.8 ms 0101 1.6 ms 25.6 ms 0110 3.2 ms 51.2 ms 0111 6.4 ms 102.4 ms 1000 12.8 ms 204.8 ms 1001 25.6 ms 409.6 ms 1010 51.2 ms 819.2 ms 1011 102.4 ms 1.6 sec 1100 204.8 ms 3.2 sec 1101 409.6 ms 6.4 sec 1110 819.2 ms 12.8 sec 1111 1.6 sec 25.6 sec 1. these values are correct if the ccf bits in the scntl3 register are set according to the valid combinations in the bit description. 2. 50 mhz clock is not supported for ultra2 scsi operation.
scsi registers 5-79 hthsf handshake to handshake timer scale factor 4 setting this bit causes this timer to shift by a factor of 16. gen[3:0] general purpose timer period [3:0] these bits select the period of the general purpose timer. the time measured is the time between enabling and disabling of the timer. when this timing is exceeded, the gen bit in the sist1 register is set. refer to table 5.8, timeout periods, on page 76 under the scsi timer zero (stime0), bits [3:0], for the available timeout periods. note: to reset a timer before it has expired and obtain repeatable delays, the time value must be written to zero ?rst, and then table 5.10 timeout periods, 40/160 mhz clock 1 hth[7:4], sel[3:0], gen[3:0] minimum timeout (40 or 160 mhz clock) 2 gensf = 0 gensf = 1 0000 disabled disabled 0001 125 m s2ms 0010 250 m s4ms 0011 500 m s8ms 0100 1 m s16ms 0101 2 ms 32 ms 0110 4 ms 64 ms 0111 8 ms 128 ms 1000 16 ms 256 ms 1001 32 ms 512 ms 1010 64 ms 1 sec 1011 128 ms 2 sec 1100 256 ms 4.1 sec 1101 512 ms 8.2 sec 1110 1.024 sec 16.4 sec 1111 2.048 sec 32.8 sec 1. these values are correct if the ccf bits in the scntl3 register are set according to the valid combinations in the bit description. 2. ultra2 scsi operation requires a quadrupled 40 mhz clock.
5-80 registers written back to the desired value. this is also required when changing from one time value to another. see chapter 2, "functional description" , for an explanation of how interrupts will be generated when the timers expire. register: 0x4a response id zero (respid0) read/write register: 0x4b response id one (respid1) read/write respid0 and respid1 contain the selection or reselection ids. in other words, these two 8-bit registers contain the id that the chip responds to on the scsi bus. each bit represents one possible id with the most signi?cant bit of respid1 representing id 15 and the least signi?cant bit of respid0 representing id 0. the scsi chip id (scid) register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the respid1 and respid0 registers. however, the chip can arbitrate with only one id value in the scid register. register: 0x4c scsi test zero (stest0) read only ssaid[3:0] scsi selected as id [7:4] these bits contain the encoded value of the scsi id that the SYM53C895 was selected or reselected as during a scsi selection or reselection phase. these bits are read only and contain the encoded value of 0C15 possible ids that could be used to select the SYM53C895. during a scsi selection or reselection phase when a valid id has been put on the bus, and the SYM53C895 responds to that id, the selected as id is written into these bits. these bits are used with the respid registers to allow response to multiple ids on the bus. 76543210 ssaid[3:0] slt art soz som 00000x11
scsi registers 5-81 slt selection response logic test 3 this bit is set when the SYM53C895 is ready to be selected or reselected. this does not take into account the bus settle delay of 400 ns. this bit is used for functional test and fault purposes. art arbitration priority encoder test 2 this bit is always set when the SYM53C895 exhibits the highest priority id asserted on the scsi bus during arbi- tration. it is primarily used for chip level testing, but it may be used during low-level mode operation to determine if the SYM53C895 has won arbitration. soz scsi synchronous offset zero this bit indicates that the current synchronous sreq/sack offset is zero. this bit is not latched and may change at any time. it is used in low-level synchronous scsi operations. when this bit is set, the SYM53C895, as an initiator, is waiting for the target to request data transfers. if the SYM53C895 is a target, then the initiator has sent the offset number of acknowledges. som (scsi synchronous offset maximum) 0 this bit indicates that the current synchronous sreq/sack offset is the maximum speci?ed by bits[3:0] in the scsi transfer register. this bit is not latched and may change at any time. it is used in low-level synchronous scsi operations. when this bit is set, the SYM53C895, as a target, is waiting for the initiator to acknowledge the data transfers. if the SYM53C895 is an initiator, then the target has sent the offset number of requests.
5-82 registers register: 0x4d scsi test one (stest1) read/write sclk scsi clock 7 setting this bit disables the external sclk (scsi clock) pin and the internal scsi clock quadrupler, and the chip uses the pci clock as the internal scsi clock. if a transfer rate of 10 mbytes/s (or 20 mbytes/s on a wide scsi bus) is to be achieved on the scsi bus, this bit must be reset and at least a 40 mhz external sclk must be provided. siso scsi isolation mode 6 this bit allows the SYM53C895 to put the scsi bidirectional and input pins into a low power mode when the scsi bus is not in use. when this bit is set, the scsi bus inputs are logically isolated from the scsi bus. r reserved [5:4] qen sclk quadrupler enable 3 set this bit to bring the scsi clock quadrupler out of the powered-down state. the default value of this bit is clear (scsi clock quadrupler powered down). set bit 2 after setting this bit, to increase the sclk frequency to 160 mhz. qsel sclk quadrupler select 2 set this bit after powering up the scsi clock quadrupler to increase the sclk frequency to 160 mhz. this bit has no effect unless bit 3 is set. r reserved [1:0] 76543210 sclk siso r qen qsel r 00xx00xx
scsi registers 5-83 5.2.0.1 quadrupling the scsi clock frequency the SYM53C895 scsi clock quadrupler increases the frequency of a 40 mhz scsi clock to 160 mhz. follow these steps to use the clock quadrupler: 1. set the sclk quadrupler enable bit (stest1, bit 3). 2. poll bit 5 of the stest4 register. the SYM53C895 sets this bit as soon as it locks in the 160 mhz frequency. the frequency lockup takes approximately 100 microseconds. 3. halt the scsi clock by setting the halt scsi clock bit (stest3 bit 5). 4. set the clock conversion factor using the scf and ccf ?elds in the scntl3 register. 5. set the sclk quadrupler select bit (stest1, bit 2). 6. clear the halt scsi clock bit. register: 0x4e (0xce) scsi test two (stest2) read/write sce scsi control enable 7 setting this bit allows all scsi control and data lines to be asserted through the scsi output control latch (socl) and scsi output data latch (sodl) registers regardless of whether the SYM53C895 is con?gured as a target or initiator. this bit should not be set during normal operation, since it could cause contention on the scsi bus. it is included for diagnostic purposes only. 76543210 sce rof dif slb szm aws ext low 00000000
5-84 registers rof reset scsi offset 6 setting this bit clears any outstanding synchronous sreq/sack offset. if a scsi gross error condition occurs, set this bit to clear the offset when a synchronous transfer does not complete successfully. the bit automatically clears itself after resetting the synchronous offset. dif scsi differential mode 5 setting this bit allows the SYM53C895 to interface properly to external differential transceivers. its only real effect is to 3-state the sbsy/, ssel/, and srst/ pads so that they can be used as pure inputs. this bit must be cleared for single-ended or lvd operation. this bit should be set in the initialization routine if the high voltage differential interface is used. slb scsi loopback mode 4 setting this bit allows the SYM53C895 to perform scsi loopback diagnostics. that is, it enables the scsi core to simultaneously perform as both initiator and target. szm scsi high-impedance mode 3 setting this bit places all the open-drain 48 ma scsi drivers into a high-impedance state. this is to allow internal loopback mode operation without affecting the scsi bus. aws always wide scsi 2 when this bit is set, all scsi information transfers are done in 16-bit wide mode. this includes data, message, command, status and reserved phases. this bit should normally be deasserted since 16-bit wide message, command, and status phases are not supported by the scsi speci?cations. ext extend sreq/sack filtering 1 lsi logic symbios tolerant scsi receiver technology includes a special digital ?lter on the sreq/ and sack/ pins that causes glitches on deasserting edges to be disregarded. setting this bit increases the ?ltering period from 30 ns to 60 ns on the deasserting edge of the sreq/ and sack/ signals.
scsi registers 5-85 this bit must never be set during fast scsi (greater than 5 mega transfers per second) operations, because a valid assertion could be treated as a glitch. this bit does not affect the ?ltering period when the ultra enable bit in the scntl3 register is set. when the SYM53C895 is executing ultra2 scsi transfers, the ?ltering period is automatically set at 8 ns. when the SYM53C895 is executing ultra scsi transfers, the ?ltering period is automatically set at 15 ns. low (scsi low level mode) 0 setting this bit places the SYM53C895 in low-level mode. in this mode, no dma operations occur, and no scripts execute. arbitration and selection may be performed by setting the start sequence bit as described in the scntl0 register. scsi bus transfers are performed by manually asserting and polling scsi signals. clearing this bit allows instructions to be executed in scsi scripts mode. note: it is not necessary to set this bit for access to the scsi bit- level registers (sodl, sbcl, and input registers). register: 0x4f (0xcf) scsi test three (stest3) read/write te tolerant enable 7 setting this bit enables the active negation portion of lsi logic symbios tolerant technology. active negation causes the scsi request, acknowledge, data, and par- ity signals to be actively deasserted, instead of relying on external pull-ups, when the SYM53C895 is driving these signals. active deassertion of these signals will occur only when the SYM53C895 is in an information transfer phase. when operating in a differential environment or at fast scsi timings, tolerant active negation should be enabled to improve setup and deassertion times. active negation is disabled after reset or when this bit is cleared. 76543210 te str hsc dsi s16 ttm csf stw 00000000
5-86 registers for more information on lsi logic symbios tolerant technology, refer to chapter 1, "introduction" . this bit must be set if the ultra enable bit in scntl3 is set. this bit must be set to use the lvd link transceivers. str scsi fifo test read 6 setting this bit places the scsi core into a test mode in which the scsi fifo can be easily read. reading the least signi?cant byte of the sodl register causes the fifo to unload. the functions are summarized in the table below. hsc halt scsi clock 5 asserting this bit causes the internal divided scsi clock to come to a stop in a glitchless manner. this bit may be used for test purposes or to lower i dd during a power down mode. this bit is used when enabling the scsi clock quadrupler. for additional information on the clock quadrupler, please see section 2.5.1, using the scsi clock quadrupler in chapter 2. dsi disable single initiator rponse 4 if this bit is set, the SYM53C895 ignores all bus-initiated selection attempts that employ the single-initiator option from scsi-1. in order to select the SYM53C895 while this bit is set, the SYM53C895 scsi id and the initiator scsi id must both be asserted. this bit should be asserted in scsi-2 systems so that a single bit error on the scsi bus is not interpreted as a single initiator response. s16 16-bit system 3 if this bit is set, all devices in the scsi system implementation are assumed to be 16 bits. this causes register name register operation fifo bits fifo function sodl read 15C0 unload sodl0 read 7C0 unload sodl1 read 15C8 none
scsi registers 5-87 the SYM53C895 to always check the parity bit for scsi ids 15C8 during bus-initiated selection or reselection, assuming parity checking has been enabled. if an 8-bit scsi device attempts to select the SYM53C895 while this bit is set, the SYM53C895 ignores the selection attempt, because the parity bit for ids 15C8 will be undriven. see the description of the enable parity checking bit in the scsi control zero (scntl0) register on page 5-17 for more information. ttm timer test mode 2 asserting this bit facilitates testing of the selection timeout, general purpose, and handshake to handshake timers by greatly reducing all three timeout periods. setting this bit starts all three timers and if the respective bits in the sien1 register are asserted, the SYM53C895 generates interrupts at timeout. this bit is intended for internal manufacturing diagnosis and should not be used. csf clear scsi fifo 1 setting this bit causes the full ?ags for the scsi fifo to be cleared. this empties the fifo. this bit is self- resetting. in addition to the scsi fifo pointers, the sidl, sodl, and sodr full bits in the scsi status zero (sstat0) and scsi status two (sstat2) registers are cleared. stw scsi fifo test write 0 setting this bit places the scsi core into a test mode in which the fifo can easily be read or written. while this bit is set, writes to the least signi?cant byte of the sodl register will cause the entire word contained in this register to be loaded into the fifo. writing the least signi?cant byte of the scsi output data latch (sodl) register causes the fifo to load. these functions are summarized in the table below: register name register operation fifo bits fifo function sodl write 15C0 load sodl0 write 7C0 load sodl1 write 15C8 none
5-88 registers register: 0x50C0x51 (0xd0C0xd1 scsi input data latch (sidl) read only this register is used primarily for diagnostic testing, programmed i/o operation, or error recovery. data received from the scsi bus can be read from this register. data can be written to the scsi output data latch (sodl) register and then read back into the SYM53C895 by reading this register to allow loopback testing. when receiving scsi data, the data ?ows into this register and out to the host fifo. this register differs from the scsi bus data lines (sbdl) register in that sidl contains latched data and the sbdl always contains exactly what is currently on the scsi data bus. reading this register causes the scsi parity bit to be checked, and causes a parity error interrupt if the data is not valid. the power-up values are indeterminate. register: 0x52 (0xd2) scsi test 4 (stest4) read only smode scsi mode [7:6] these bits contain the encoded value of the scsi oper- ating mode that is indicated by the voltage level sensed at the diffsens pin. the incoming scsi signal goes to a pair of analog comparators that determine the voltage window of the diffsens signal. these voltage windows indicate low voltage differential, single-ended, or high- power differential operation. the bit values are de?ned in table 5.11 . 76543210 smode lock r r r r r xx0xxxxx
scsi registers 5-89 lock (frequency lock 5 this bit is used when enabling the scsi clock quadrupler, which allows the SYM53C895 to transfer data at ultra2 scsi rates. poll this bit for a 1 to determine that the clock quadrupler has locked to 160 mhz. for more information on enabling the clock quadrupler, refer to the descriptions about the scsi test one (stest1) register, bits 2 and 3 on page 5-82 . r reserved [4:0] register: 0x54C0x55 (0xd4C0xd5) scsi output data latch (sodl) read/write this register is used primarily for diagnostic testing or programmed i/o operation. data written to this register is asserted onto the scsi data bus by setting the assert data bus bit in the scntl1 register. this register sends data using programmed i/o. data ?ows through this register when sending data in any mode. it also writes to the synchronous data fifo when testing the chip. the power-up value of this register is indeterminate. register: 0x58C0x59 (0xd8C0xd9) scsi bus data lines (sbdl) read only this register contains the scsi data bus status. even though the scsi data bus is active low, these bits are active high. the signal status is not table 5.11 diffsens voltage levels and scsi operating modes bit [7:6] operating mode 00 not possible 01 high voltage differential or powered down (for high voltage differential mode, the dif bit must also be set) 10 single-ended 11 low voltage differential scsi
5-90 registers latched and is a true representation of exactly what is on the data bus at the time the register is read. this register is used when receiving data through programmed i/o. this register can also be used for diagnostic testing or in low-level mode. the power-up value of this register is indeterminate. register: 0x5cC0x5f (0xdcC0xdf) scratch register b (scratchb) read/write this is a general purpose user de?nable scratch pad register. apart from cpu access, only register read/write and memory moves directed at the scratch register will alter its contents. the SYM53C895 cannot fetch scripts instructions from this location. when bit 3 in the ctest2 register is set, this register contains the base address for the 4 kbyte internal ram. setting ctest2 bit 3 only causes the base address to appear in the scratchb register; any information that was previously in the register remains intact. any writes to this register while the bit is set passes through to the actual scratchb register. the power-up values are indeterminate. register: 0x60C0x7f (0xe0C0xff) scratch registers c-j (scratchc C scratchj) read/write these registers are general-purpose scratch registers for user-de?ned functions. the SYM53C895 cannot fetch scripts instructions from this location.the power-up value of these registers is indeterminate.
symbios SYM53C895 pci to ultra2 scsi i/o processor 6-1 chapter 6 scsi scripts instruction set the SYM53C895 contains a scsi scripts processor that permits both dma and scsi commands to be fetched from host memory or internal scripts ram. algorithms written in scsi scripts control the actions of the scsi and dma cores. the scripts processor executes complex scsi bus sequences independently of the host cpu. this chapter describes the scsi scripts instruction set used to write these algorithms. this chapter includes these sections, which describe the bene?ts and use of scsi scripts instructions: section 6.1, low-level register interface mode, page 6-2 section 6.2, high-level scsi scripts mode, page 6-2 section 6.3, block move instruction, page 6-6 section 6.4, i/o instruction, page 6-13 section 6.5, read/write instructions, page 6-22 section 6.6, transfer control instruction, page 6-26 section 6.7, memory move instructions, page 6-33 section 6.8, load and store instructions, page 6-36 after power up and initialization of the SYM53C895, the chip can be operated in the low-level register interface mode or in the high-level scsi scripts mode.
6-2 scsi scripts instruction set 6.1 low-level register interface mode with the low-level register interface mode, the user has access to the dma control logic and the scsi bus control logic. an external processor has access to the scsi bus signals and the low-level dma signals, which allows creation of complicated board level test algorithms. the low-level interface is useful for backward compatibility with scsi devices that require certain unique timings or bus sequences to operate properly. another feature allowed at the low-level is loopback testing. in loopback mode, the scsi core can be directed to talk to the dma core to test internal data paths all the way out to the chip pins. 6.2 high-level scsi scripts mode to operate in the scsi scripts mode, the SYM53C895 requires only a scripts start address. the start address must be at a dword (four byte) boundary to align all the following scripts at a dword boundary since all scripts are 8 or 12 bytes long. instructions are fetched until an interrupt instruction is encountered, or until an unexpected event (such as a hardware error) causes an interrupt to the external processor. once an interrupt is generated, the SYM53C895 halts all operations until the interrupt is serviced. then, the start address of the next scripts instruction may be written to the dma scripts pointer register to restart the automatic fetching and execution of instructions. the scsi scripts mode of execution allows the SYM53C895 to make decisions based on the status of the scsi bus, which off-loads the microprocessor from servicing the numerous interrupts inherent in i/o operations. given the rich set of scsi-oriented features included in the instruction set, and the ability to re-enter the scsi algorithm at any point, this high- level interface is all that is required for both normal and exception conditions. switching to low-level mode for error recovery should never be required.
high-level scsi scripts mode 6-3 table 6.1 shows the types of scripts instructions are implemented in the SYM53C895: each instruction consists of two or three 32-bit words. the ?rst 32-bit word is always loaded into the dma command (dcmd) and dma byte counter (dbc) registers, the second into the dma scripts pointer save (dsps) register. the third word, used only by memory move instructions, is loaded into the temporary (temp) shadow register. in an indirect i/o or move instruction, the ?rst two 32-bit opcode fetches are followed by one or two more 32-bit fetch cycles. 6.2.1 sample operation this sample operation describes execution of a scripts instruction for a block move instruction. 1. the host cpu, through programmed i/o, gives the dma scripts pointer (dsp) register (in the operating register ?le) the starting address in main memory that points to a scsi scripts program for execution. table 6.1 scripts instructions instruction description block move block move instruction moves data between the scsi bus and memory i/o or read/write i/o or read/write instructions cause the SYM53C895 to trigger common scsi hardware sequences, or to move registers transfer control transfer control instruction allows scripts instructions to make decisions based on real time scsi bus conditions memory move memory move instruction causes the SYM53C895 to execute block moves between different parts of main memory load and store load and store instructions provide a more ef?cient way to move data to/from memory from/to an internal register in the chip without using the memory move instruction
6-4 scsi scripts instruction set 2. loading the dsp register causes the SYM53C895 to fetch its ?rst instruction at the address just loaded. this is from main memory or the internal ram, depending on the address. 3. the SYM53C895 typically fetches two dwords (64 bits) and decodes the high order byte of the ?rst longword as a scripts instruction. if the instruction is a block move, the lower three bytes of the ?rst longword are stored and interpreted as the number of bytes to be moved. the second longword is stored and interpreted as the 32-bit beginning address in main memory to which the move is directed. 4. for a scsi send operation, the SYM53C895 waits until there is enough space in the dma fifo to transfer a programmable size block of data. for a scsi receive operation, it waits until enough data is collected in the dma fifo for transfer to memory. at this point, the SYM53C895 requests use of the pci bus again to transfer the data. 5. when the SYM53C895 is granted the pci bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrements the internally stored remaining byte count, increments the address pointer, and then releases the pci bus. the SYM53C895 stays off the pci bus until the fifo can again hold (for a write) or has collected (for a read) enough data to repeat the process. the process repeats until the internally stored byte count has reached zero. the SYM53C895 releases the pci bus and then performs another scripts instruction fetch cycle, using the incremented stored address maintained in the dma scripts pointer register. execution of scripts instructions continues until an error condition occurs or an interrupt scripts instruction is received. at this point, the SYM53C895 interrupts the host cpu and waits for further servicing by the host system. it can execute independent block move instructions specifying new byte counts and starting locations in main memory. in this manner, the SYM53C895 performs scatter/gather operations on data without requiring help from the host program, generating a host interrupt, or requiring an external dma controller to be programmed. figure 6.1 shows a scripts overview.
high-level scsi scripts mode 6-5 figure 6.1 scripts overview system processor system memory scsi initiator write example ta bl e byte count address byte count address byte count address byte count address data structure message buffer command buffer data buffer status buffer b u s s y s t e m write dsa write dsp fetch scripts data SYM53C895 scsi bus block diagram in chapter 2 for details, see p c i x select atn 0, alt_addr x move from identify_msg_buf, when msg_out x move from data_buf when data_out x move from stat_in_buf, when status x move scntl2 & 7f to scntl2 x clear ack x wait disconnect alt2 x int 10
6-6 scsi scripts instruction set 6.3 block move instruction performing a block move instruction, bit 5, source i/o - memory enable (siom) and bit 4, destination i/o - memory enable (diom) in the dma mode (dmode) register determine whether the source/destination address resides in memory or i/o space. when data is being moved onto the scsi bus, siom controls whether that data comes from i/o or memory space. when data is being moved off of the scsi bus, diom controls whether that data goes to i/o or memory space. 6.3.1 first dword it[1:0] instruction type - block move [31:30] the it bit con?guration (00) de?nes a block move instruction type. ia indirect addressing 29 this bit determines if addressing is direct or indirect. if ia bit is (0), use destination ?eld as an address (direct addressing). if ia bit is (1), use destination ?eld as a pointer to an address (indirect addressing). when this bit is zero, user data is moved to or from the 32-bit data start address for the block move instruction. the value is loaded into the chip address register and incremented as data is transferred. the address of the data to move is in the second dword of this instruction. when this bit is one, the 32-bit user data start address for the block move is the address of a pointer to the actual data buffer address. the value at the 32-bit start address is loaded into the chip dma next address for data (dnad) register using a third longword fetch (4-byte transfer across the host computer bus). 31 30 29 28 27 26 24 23 16 15 8 7 0 dcmd (dma command) register dbc (dma byte counter) register it[1:0] ia tia opc scsip[2:0] tc (transfer counter) [23:0] 0 0 x x x x x x xxxxxxxxxxxxxxxxxxxxxxxx
block move instruction 6-7 direct addressing the byte count and absolute address are: indirect addressing use the fetched byte count, but fetch the data address from the address in the instruction. . once the data pointer address is loaded, it is executed as when the chip operates in the direct mode. this indirect feature allows a table of data buffer addresses to be speci?ed. using the symbios scsi scripts assembler, the table offset is placed in the script at compile time. then at the actual data transfer time, the offsets are added to the base address of the data address table by the external processor. the logical i/o driver builds a structure of addresses for an i/o rather than treating each address individually. this feature makes it possible to locate scsi scripts in a prom. note: do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. tia table indirect 28 32-bit addressing when this bit is set, the 24-bit signed value in the start address of the move is treated as a relative displacement from the value in the data structure address (dsa) register. both the transfer count and the source/ destination address are fetched from this location. use the signed integer offset in bits [23:0] of the second four bytes of the instruction, added to the value in the data structure address (dsa) register, to fetch ?rst the byte count and then the data address. the signed value is combined with the data structure base address to generate the physical address used to fetch values from the data structure. sign-extended values of all ones for negative values are allowed, but bits [31:24] are ignored. command byte count address of data command byte count address of pointer to data
6-8 scsi scripts instruction set . note: do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. prior to the start of an i/o, the data structure base address (dsa) register should be loaded with the base address of the i/o data structure. the address may be any address on a longword boundary. after a table indirect opcode is fetched, the dsa is added to the 24-bit signed offset value from the op code to generate the address of the required data; both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. for a move instruction, the 24-bit byte count is fetched from system memory. then the 32-bit physical address is brought into the SYM53C895. execution of the move begins at this point. scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any longword boundary and may cross system segment boundaries. there are two restrictions on the placement of pointer data in system memory: the eight bytes of data in the move instruction must be contiguous, as shown below, and indirect data fetches are not available during execution of a memory to memory dma operation. opc op code 27 this 1-bit op code ?eld de?nes the type of block move (move) instruction to be preformed in target and initiator mode. command not used dont care table offset 00 byte count physical data address
block move instruction 6-9 target mode in target mode, the op code bit de?nes the following operations: these instructions perform the following steps: 1. the SYM53C895 veri?es that it is connected to the scsi bus as a target before executing this instruction. 2. the SYM53C895 asserts the scsi phase signals (smsg/, sc_d/, and si_o/) as de?ned by the phase field bits in the instruction. 3. if the instruction is for the command phase, the SYM53C895 receives the ?rst command byte and decodes its scsi group code. a) if the scsi group code is either group 0, group 1, group 2, or group 5, and if the vendor unique enhancement 1 (vue1) bit (scntl2 bit 1) is clear, then the SYM53C895 overwrites the dbc register with the length of the command descriptor block: 6, 10, or 12 bytes. b) if the vendor unique enhancement 1 (vue1) bit (scntl2 bit 1) is set, the SYM53C895 receives the number of bytes in the byte count regardless of the group code. c) if the vendor unique enhancement 1 bit is clear and group code is vendor unique, the SYM53C895 receives the number of bytes in the count. d) if any other group code is received, the dbc register is not modi?ed and the SYM53C895 requests the number of bytes speci?ed in the dbc register. if the dbc register contains 0x000000, an illegal instruction interrupt is generated. 4. the SYM53C895 transfers the number of bytes speci?ed in the dbc register starting at the address speci?ed in the dnad register. if the opcode bit is set and a data transfer ends on an odd byte boundary, the SYM53C895 opc instruction de?ned 0 move/move64 1 chmov/chmov64
6-10 scsi scripts instruction set stores the last byte in the scsi wide residue data register during a receive operation. this byte is combined with the ?rst byte from the subsequent transfer so that a wide transfer can be completed. 5. if the satn/ signal is asserted by the initiator or a parity error occurred during the transfer, the transfer can optionally be halted and an interrupt generated. the disable halt on parity error or atn bit in the scntl1 register controls whether the SYM53C895 halts on these conditions immediately, or waits until completion of the current move. initiator mode in target mode, the op code bit de?nes the following operations: these instructions perform the following steps: 1. the SYM53C895 veri?es that it is connected to the scsi bus as an initiator before executing this instruction. 2. the SYM53C895 waits for an unserviced phase to occur. an unserviced phase is any phase (with sreq/ asserted) for which the SYM53C895 has not yet transferred data by responding with a sack/. 3. the SYM53C895 compares the scsi phase bits in the dma command (dcmd) register with the latched scsi phase lines stored in the scsi status one (sstat1) register. these phase lines are latched when sreq/ is asserted. 4. if the scsi phase bits match the value stored in the scsi status one (sstat1) register, the SYM53C895 transfers the number of bytes speci?ed in the dma byte counter (dbc) register starting at the address pointed to by the dnad register. if the opcode bit is cleared and a data transfer ends on an odd byte boundary, the SYM53C895 stores the last byte in the scsi wide residue (swide) opc instruction de?ned 0 chmov 1move
block move instruction 6-11 register during a receive operation, or in the scsi output data latch (sodl) register during a send operation. this byte is combined with the ?rst byte from the subsequent transfer so that a wide transfer can complete. 5. if the scsi phase bits do not match the value stored in the scsi status one (sstat1) register, the SYM53C895 generates a phase mismatch interrupt and the instruction is not executed. 6. during a message-out phase, after the SYM53C895 has performed a select with attention (or satn/ is manually asserted with a set atn instruction), the SYM53C895 deasserts satn/ during the ?nal sreq/sack/ handshake. 7. when the SYM53C895 is performing a block move for message-in phase, it does not deassert the sack/ signal for the last sreq/sack/ handshake. clear the sack/ signal using the clear sack i/o instruction. scsip[2:0] scsi phase [26:24] this 3-bit ?eld de?nes the scsi information transfer phase. when the SYM53C895 operates in initiator mode, these bits are compared with the latched scsi phase bits in the scsi status one (sstat1) register. when the SYM53C895 operates in target mode, it asserts the phase de?ned in this ?eld. table 6.2 describes the possible combinations and the corresponding scsi phase. table 6.2 scsi information transfer phase msg c_d i_o scsi phase 0 0 0 data-out 0 0 1 data-in 0 1 0 command 0 1 1 status 1 0 0 reserved-out 1 0 1 reserved-in 1 1 0 message-out 1 1 1 message-in
6-12 scsi scripts instruction set tc[23:0] transfer counter [23:0] this 24-bit ?eld speci?es the number of data bytes to be moved between the SYM53C895 and system memory. the ?eld is stored in the dma byte counter (dbc) register. when the SYM53C895 transfers data to/from memory, the dbc register is decremented by the number of bytes transferred. in addition, the dnad register is incremented by the number of bytes transferred. this process is repeated until the dbc register is decremented to zero. at this time, the SYM53C895 fetches the next instruction. if bit 28 is set, indicating table indirect addressing, this ?eld is not used. the byte count is instead fetched from a table pointed to by the dsa register. 6.3.2 second dword start address [31:0] this 32-bit ?eld speci?es the starting address of the data to move to/from memory. this ?eld is copied to the dnad register. when the SYM53C895 transfers data to or from memory, the dnad register is incremented by the num- ber of bytes transferred. when bit 29 is set, indicating indirect addressing, this address is a pointer to an address in memory that points to the data location. when bit 28 is set, indicating table indirect addressing, the value in this ?eld is an offset into a table pointed to by the dsa. the table entry contains byte count and address information. 31 24 23 16 15 8 7 0 dsps (dma scripts pointer save) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
i/o instruction 6-13 6.4 i/o instruction i/o instructions perform the following scsi operations in target and initiator mode. these i/o operations are chosen with the op code bits in the dcmd register. all reserved bits are shaded. this section describes these i/o operations. 6.4.1 first dword it[1:0] instruction type - i/o instruction [31:30] the it bit con?guration (01) de?nes an i/o instruction type. opc[2:0] op code [29:27] the op code bit con?gurations de?ne the i/o operation performed but the op code bit meanings change in target mode compared to initiator mode. op code bit con?guration (101, 110, and 111) are considered read/write instructions, and are described in that section. this section describes target mode operations. opc2 opc1 opc0 target mode initiator mode 0 0 0 reselect select 0 0 1 disconnect wait disconnect 0 1 0 wait select wait reselect 0 1 1 set set 1 0 0 clear clear 31 30 29 27 26 25 24 23 20 19 16 15 11 10 9 8 7 6 5 4 3 2 0 dcmd (dma command) register dbc (dma byte counter) register it[1:0] opc[2:0] ra ti sel r endid[3:0] r cc tm r ack r atn r 0 1 x x x x x x 0000xxxx00000 x x 00 x 00 x 000
6-14 scsi scripts instruction set target mode reselect instruction 1. the SYM53C895 arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. 2. if the SYM53C895 wins arbitration, it attempts to reselect the scsi device whose id is de?ned in the destination id ?eld of the instruction. once the SYM53C895 wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. this way the scripts can move on to the next instruction before the reselection completes. it continues executing scripts until a script that requires a response from the initiator is encountered. 3. if the SYM53C895 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dnad register. manually set the SYM53C895 to initiator mode if it is reselected, or to target mode if it is selected. disconnect instruction the SYM53C895 disconnects from the scsi bus by deasserting all scsi signal outputs. opc2 opc1 opc0 instruction de?ned 0 0 0 reselect 0 0 1 disconnect 0 1 0 wait select 011set 1 0 0 clear
i/o instruction 6-15 wait select instruction 1. if the SYM53C895 is selected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. 2. if reselected, the SYM53C895 fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dnad register. manually set the SYM53C895 to initiator mode when it is reselected. 3. if the cpu sets the sigp bit in the interrupt status (stat0) register, the SYM53C895 aborts the wait select instruction and fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dnad register. set instruction when the sack/ or satn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. do not set sack/ or satn/ except for testing purposes. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the arithmetic logic unit (alu) is set. note: none of the signals are set on the scsi bus in target mode. clear instruction when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output control latch (socl) register. do not set sack/ or satn/ except for testing purposes. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. note: none of the signals are cleared on the scsi bus in the target mode.
6-16 scsi scripts instruction set initiator mode select instruction 1. the SYM53C895 arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. 2. if the SYM53C895 wins arbitration, it attempts to select the scsi device whose id is de?ned in the destination id ?eld of the instruction. once the SYM53C895 wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. this way the scripts can move to the next instruction before the selection completes. it continues executing scripts until a script that requires a response from the target is encountered. 3. if the SYM53C895 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dnad register. manually set the SYM53C895 to initiator mode if it is reselected, or to target mode if it is selected. 4. if the select with satn/ ?eld is set, the satn/ signal is asserted during the selection phase. wait disconnect instruction the SYM53C895 waits for the target to perform a legal disconnect from the scsi bus. a legal disconnect occurs when sbsy/ and ssel/ are inactive for a minimum of one bus free delay (400 ns), after the SYM53C895 receives a disconnect message or a command complete message. opc2 opc1 opc0 instruction de?ned 0 0 0 select 0 0 1 wait disconnect 0 1 0 wait reselect 0 1 1 set 1 0 0 clear
i/o instruction 6-17 wait reselect instruction 1. if the SYM53C895 is selected before being reselected, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dnad register. manually set the SYM53C895 to target mode when it is selected. 2. if the SYM53C895 is reselected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. 3. if the cpu sets the sigp bit in the interrupt status (istat0) register, the SYM53C895 aborts the wait reselect instruction and fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dnad register. set instruction when the sack/ or satn/ bits are set, the corresponding bits in the scsi output cntrol latch (socl) register are set. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the alu is set. clear instruction when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output control latch (socl) register. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. ra relative addressing mode 26 when this bit is set, the 24-bit signed value in the dnad register is used as a relative displacement from the current dma scripts pointer (dsp) address. use this bit only in conjunction with the select, reselect, wait select, and wait reselect instructions. the select and reselect instructions can contain an absolute alternate jump address or a relative transfer address.
6-18 scsi scripts instruction set ti table indirect mode 25 when this bit is set, the 24-bit signed value in the dma byte counter (dbc) register is added to the value in the data structure address (dsa) register, and used as an offset relative to the value in the data structure address (dsa) register. the scsi control three (scntl3) value, scsi id, synchronous offset and synchronous period are loaded from this address. prior to the start of an i/o, load the data structure address (dsa) with the base address of the i/o data structure. any address on a dword boundary is allowed. after a table indirect op code is fetched, the data structure address (dsa) is added to the 24-bit signed offset value from the op code to generate the address of the required data. both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any dword boundary and may cross system segment boundaries. there are two restrictions on the placement of data in system memory: the i/o data structure must lie within the 8 mbytes above or below the base address. an i/o command structure must have all four bytes contiguous in system memory, as shown below. the offset/period bits are ordered as in the scsi transfer (sxfer) register. the con?guration bits are ordered as in the scsi control three (scntl3) register. use bit 25 only in conjunction with the select, reselect, wait select, and wait reselect instructions. use bits 25 and 26 individually or in combination to produce the following conditions: con?g id offset/period 00
i/o instruction 6-19 direct uses the device id and physical address in the instruction. table indirect uses the physical jump address, but fetches data using the table indirect method. relative uses the device id in the instruction, but treats the alternate address as a relative jump. table relative treats the alternate jump address as a relative jump and fetches the device id, synchronous offset, and synchronous period indirectly. the value in bits [23:0] of the ?rst four bytes of the scripts instruction is added to the data structure base address to form the fetch address. bit 25 bit 26 addressing mode 0 0 direct 0 1 table indirect 1 0 relative 1 1 table relative command id not used not used absolute alternate address command table offset absolute alternate address command id not used not used absolute jump offset command table offset alternate jump offset
6-20 scsi scripts instruction set sel select with atn/ 24 this bit speci?es whether satn/ is asserted during the selection phase when the SYM53C895 is executing a select instruction. when operating in initiator mode, set this bit for the select instruction. if this bit is set on any other i/o instruction, an illegal instruction interrupt is generated. r reserved [23:20] endid[3:0] encoded scsi destination id [19:16] this 4-bit ?eld speci?es the destination scsi id for an i/o instruction. r reserved [15:11] cc set/clear carry 10 this bit is used in conjunction with a set or clear instruction to set or clear the carry bit. setting this bit with a set instruction asserts the carry bit in the alu. clearing this bit with a clear instruction deasserts the carry bit in the alu. tm set/clear target mode 9 this bit is used in conjunction with a set or clear instruction to set or clear target mode. setting this bit with a set instruction con?gures the SYM53C895 as a target device (this sets bit 0 of the scsi control zero (scntl0) register). clearing this bit with a clear instruction con?gures the SYM53C895 as an initiator device (this clears bit 0 of the scntl0 register). r reserved [8:7] ack set/clear sack/ 6 r reserved [5:4] atn set/clear satn/ 3 these two bits (6 and 3)are used in conjunction with a set or clear instruction to assert or deassert the corre- sponding scsi control signal. bit 6 controls the scsi sack/ signal. bit 3 controls the scsi satn/ signal.
i/o instruction 6-21 the set instruction asserts sack/ and/or satn/ on the scsi bus. the clear instruction deasserts sack/ and/or satn/ on the scsi bus. the corresponding bit in the scsi output control latch (socl) register is set or cleared depending on the instruction used. since sack/ and satn/ are initiator signals, they are not asserted on the scsi bus unless the SYM53C895 is operating as an initiator or the scsi loopback enable bit is set in the scsi test two (stest2) register. the set/clear scsi ack/, atn/ instruction is used after message phase block move operations to give the initiator the opportunity to assert attention before acknowledging the last message byte. for example, if the initiator wishes to reject a message, it issues an assert scsi atn instruction before a clear scsi ack instruction. r reserved [2:0] 6.4.2 second dword sa start address [31:0] this 32-bit ?eld contains the memory address to fetch the next instruction if the selection or reselection fails. if relative or table relative addressing is used, this value is a 24-bit signed offset relative to the current dma scripts pointer (dsp) register value. 31 24 23 16 15 8 7 0 dsps (dma scripts pointer save) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
6-22 scsi scripts instruction set 6.5 read/write instructions the read/write instruction supports addition, subtraction, and comparison of two separate values within the chip. it performs the desired operation on the speci?ed register and the scsi first byte received (sfbr) register, then stores the result back to the speci?ed register or the sfbr. if the com bit dma control (dcntl bit 0) is cleared, read/write instructions can not be used. 6.5.1 first dword it[1:0] instruction type - read/write instruction [31:30] the con?guration of the it bits, the op code bits and the operator bits de?ne the read/write instruction type. the con?guration of all these bits determine which instruction is currently selected. opc[2:0] op code [29:27] the combinations of these bits determine if the instruction is a read/write or an i/o instruction. op codes 0b000 through 0b100 are considered i/o instructions. oper[2:0] operator [26:24] these bits are used in conjunction with the opcode bits to determine which instruction is currently selected. refer to table 6.1 for ?eld de?nitions. d8 use data8/sfbr 23 when this bit is set, scsi first byte received (sfbr) is used instead of the data8 value during a read-modify- write instruction (see table 6.1 ). this allows the user to add two register values. 31 30 29 27 26 24 23 22 16 15 8 7 0 dcmd (dma command) register dbc (dma byte counter) register it[1:0] opc[2:0] oper[2:0] d8 a[6:0] immd reserved - must be 0 0 1 x x x x x x x xxxxxxxxxxxxxxx00000000
read/write instructions 6-23 a[6:0] register address - a[6:0] [22:16] it is possible to change register values from scripts in read-modify-write cycles or move to/from scsi first byte received (sfbr) cycles. a[6:0] selects an 8-bit source/destination register within the SYM53C895. immd immediate data [15:8] this 8-bit value is used as a second operand in logical and arithmetic functions. a7 upper register address line [a7] 7 this bit is used to access registers 0x80C0xff. r reserved [6:0] 6.5.2 second dword destination address [31:0] this ?eld contains the 32-bit destination address where the data is to move. 6.5.3 read-modify-write cycles during these cycles the register is read, the selected operation is performed, and the result is written back to the source register. the add operation is used to increment or decrement register values (or memory values if used in conjunction with a memory to register move operation) for use as loop counters. subtraction is not available when scsi first byte received (sfbr) is used instead of data8 in the instruction syntax. to subtract one value from another when using sfbr, ?rst xor the value to subtract (subtrahend) with 0xff, and add 1 to the resulting value. this creates the 2s compliment of the subtrahend. the two values are then added to obtain the difference. 31 24 23 16 15 8 7 0 dsps (dma scripts pointer save) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
6-24 scsi scripts instruction set 6.5.4 move to/from sfbr cycles all operations are read-modify-writes. however, two registers are involved, one of which is always the scsi first byte received (sfbr). see table 6.3 for these read/write insturctions. the possible functions of this instruction are: write one byte (value contained within the scripts instruction) into any chip register. move to/from the scsi first byte received (sfbr) from/to any other register. alter the value of a register with and, or, add, xor, shift left, or shift right operators. after moving values to the scsi first byte received (sfbr), the compare and jump, call, or similar instructions are used to check the value. a move to sfbr followed by a move from sfbr is used to perform a register to register move. table 6.3 read/write instructions operator op code 111 read modify write op code 110 move to sfbr op code 101 move from sfbr 000 move data into register. syntax: move data8 to rega move data into scsi first byte received (sfbr) register. syntax: move data8 to sfbr move data into register. syntax: move data8 to rega 001 1 shift register one bit to the left and place the result in the same register. syntax: move rega shl rega shift register one bit to the left and place the result in the scsi first byte received (sfbr) register. syntax: move rega shl sfbr shift the sfbr register one bit to the left and place the result in the register. syntax: move sfbr shl rega 010 or data with register and place the result in the same register. syntax: move rega | data8 to rega or data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega | data8 to sfbr or data with sfbr and place the result in the register. syntax: move sfbr | data8 to rega
read/write instructions 6-25 miscellaneous notes: - substitute the desired register name or address for rega in the syntax examples. - data8 indicates eight bits of data. - use sfbr instead of data8 to add two register values. 011 xor data with register and place the result in the same register. syntax: move rega xor data8 to rega xor data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega xor data8 to sfbr xor data with sfbr and place the result in the register. syntax: move sfbr xor data8 to rega 100 and data with register and place the result in the same register. syntax: move rega & data8 to rega and data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega & data8 to sfbr and data with sfbr and place the result in the register. syntax: move sfbr & data8 to rega 101 1 shift register one bit to the right and place the result in the same register. syntax: move rega shr rega shift register one bit to the right and place the result in the scsi first byte received (sfbr) register. syntax: move rega shr sfbr shift the sfbr register one bit to the right and place the result in the register. syntax: move sfbr shr rega 110 add data to register without carry and place the result in the same register. syntax: move rega + data8 to rega add data to register without carry and place the result in the scsi first byte received (sfbr) register. syntax: move rega + data8 to sfbr add data to sfbr without carry and place the result in the register. syntax: move sfbr + data8 to rega 111 add data to register with carry and place the result in the same register. syntax: move rega + data8 to rega with carry add data to register with carry and place the result in the scsi first byte received (sfbr) register. syntax: move rega + data8 to sfbr with carry add data to sfbr with carry and place the result in the register. syntax: move sfbr + data8 to rega with carry 1. data is shifted through the carry bit and the carry bit is shifted into the data byte. table 6.3 read/write instructions (cont.) operator op code 111 read modify write op code 110 move to sfbr op code 101 move from sfbr
6-26 scsi scripts instruction set 6.6 transfer control instruction this section describes the transfer control instructions. the con?guration of the op code bits de?ne which transfer control instruction to perform. 6.6.1 first dword it[1:0] instruction type - transfer control instruction[31:30] the it bit con?guration (10) de?nes the transfer control instruction type. opc [2:0] op code [29:27] this 3-bit ?eld speci?es the type of transfer control instruction to execute. all transfer control instructions can be conditional. they can be dependent on a true/false comparison of the alu carry bit or a comparison of the scsi information transfer phase with the phase ?eld, and/or a comparison of the first byte received with the data compare ?eld. each instruction can operate in initiator or target mode. transfer control instructions are shown in table 6.4 . 31 30 29 27 26 24 23 22 21 20 19 18 17 16 15 8 7 0 dcmd (dma command) register dbc (dma byte counter) register it[1:0] opc[2:0] scsip[2:0] ra r ct if jmp cd cp wvp dcm-data compare mask dcv-data compare value 1 0 x x x x x x x 0 x x x x x x xxxxxxxxxxxxxxxx table 6.4 transfer control instructions opc2 opc1 opc0 instruction de?ned 000jump 0 0 1 call 0 1 0 return 0 1 1 interrupt 1 x x reserved
transfer control instruction 6-27 jump instruction the SYM53C895 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare and true/false bit ?elds. if the comparisons are true, then it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register. the dsp register now contains the address of the next instruction. if the comparisons are false, the SYM53C895 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register, leaving the instruction pointer unchanged. call instruction the SYM53C895 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register and that address value becomes the address of the next instruction. when the SYM53C895 executes a call instruction, the instruction pointer contained in the dsp register is stored in the temporary (temp) register. since the temp register is not a stack and can only hold one dword, nested call instructions are not allowed. if the comparisons are false, the SYM53C895 fetches the next instruction from the address pointed to by the dsp register and the instruction pointer is not modi?ed. return instruction the SYM53C895 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register. that address value becomes the address of the next instruction.
6-28 scsi scripts instruction set when a return instruction is executed, the value stored in the temporary (temp) register is returned to the dsp register. the SYM53C895 does not check to see whether the call instruction has already been executed. it does not generate an interrupt if a return instruction is executed without previously executing a call instruction. if the comparisons are false, the SYM53C895 fetches the next instruction from the address pointed to by the dsp register and the instruction pointer is not modi?ed. interrupt instruction the SYM53C895 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, the SYM53C895 generates an interrupt by asserting the irq/ signal. the 32-bit address ?eld stored in the dma scripts pointer save (dsps) register can contain a unique interrupt service vector. when servicing the interrupt, this unique status code allows the interrupt service routine to quickly identify the point at which the interrupt occurred. the SYM53C895 halts and the dma scripts pointer (dsp) register must be written to before starting any further operation. interrupt on the fly instruction the SYM53C895 can do a true/false comparison of the alu carry bit or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, and the interrupt-on-the-fly bit (interrupt status (istat0) bit 2) is set, the SYM53C895 asserts the interrupt-on-the-fly bit. scsip[2:0] scsi phase [26:24] this 3-bit ?eld corresponds to the three scsi bus phase signals that are compared with the phase lines latched when sreq/ is asserted. comparisons can be performed to determine the scsi phase actually being driven on the scsi bus. table 6.5 describes the possible
transfer control instruction 6-29 combinations and their corresponding scsi phase. these bits are only valid when the SYM53C895 is operating in initiator mode. clear these bits when the SYM53C895 is operating in target mode. ra relative addressing mode 23 when this bit is set, the 24-bit signed value in the dma scripts pointer save (dsps) register is used as a relative offset from the current dma scripts pointer (dsp) address (which is pointing to the next instruction, not the one currently executing). the relative mode does not apply to return and interrupt scripts. jump/call an absolute address start execution at the new absolute address. jump/call a relative address start execution at the current address plus (or minus) the relative offset. table 6.5 scsi phase comparisons msg c/d i/o scsi phase 0 0 0 data-out 0 0 1 data-in 0 1 0 command 0 1 1 status 1 0 0 reserved-out 1 0 1 reserved-in 1 1 0 message-out 1 1 1 message-in command condition codes absolute alternate address command condition codes dont care alternate jump offset
6-30 scsi scripts instruction set the scripts program counter is a 32-bit value pointing to the script currently under execution by the SYM53C895. the next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the jump or call instruction. because it is signed (2s compliment), the jump can be forward or backward. a relative transfer can be to any address within a 16 mbyte segment. the program counter is combined with the 24-bit signed offset (using addition or subtraction) to form the new execution address. scripts programs may contain a mixture of direct jumps and relative jumps to provide maximum versatility when writing scripts. for example, major sections of code can be accessed with far calls using the 32-bit physical address, then local labels can be called using relative transfers. if a script is written using only relative transfers it does not require any run time alteration of physical addresses, and can be stored in and executed from a prom. r reserved 22 ct carry test 21 when this bit is set, decisions based on the alu carry bit can be made. true/false comparisons are legal, but data compare and phase compare are illegal. if interrupt-on-the-fly 20 when this bit is set, the interrupt instruction does not halt the scripts processor. once the interrupt occurs, the interrupt-on-the-fly bit (interrupt status (istat0) bit 2) is asserted. jmp jump if true/false 19 this bit determines whether the SYM53C895 branches when a comparison is true or when a comparison is false. this bit applies to phase compares, data compares, and carry tests. if both the phase compare and data compare bits are set, then both compares must be true to branch on a true condition. both compares must be false to branch on a false condition.
transfer control instruction 6-31 cd compare data 18 when this bit is set, the ?rst byte received from the scsi data bus (contained in the scsi first byte received (sfbr) register) is compared with the data to be compared field in the transfer control instruction. the wait for valid phase bit controls when this compare occurs. the jump if true/false bit determines the condition (true or false) to branch on. cp compare phase 17 when the SYM53C895 is in initiator mode, this bit controls phase compare operations. when this bit is set, the scsi phase signals (latched by sreq/) are compared to the phase field in the transfer control instruction. if they match, the comparison is true. the wait for valid phase bit controls when the compare occurs. when the SYM53C895 is operating in target mode and this bit is set it tests for an active scsi satn/ signal. wvp wait for valid phase 16 if the wait for valid phase bit is set, the SYM53C895 waits for a previously unserviced phase before comparing the scsi phase and data. if the wait for valid phase bit is cleared, the SYM53C895 compares the scsi phase and data immediately. dcm data compare mask [15:8] the data compare mask allows a script to test certain bits within a data byte. during the data compare, if any mask bits are set, the corresponding bit in the scsi first byte received (sfbr) data byte is ignored. for instance, a mask of 0b01111111 and data compare value of 0b1xxxxxxx allows the scripts processor to determine whether or not the high order bit is set while ignoring the remaining bits. bit 19 result of compare action 0 false jump taken 0 true no jump 1 false no jump 1 true jump taken
6-32 scsi scripts instruction set dcv data compare value [7:0] this 8-bit ?eld is the data compared against the scsi first byte received (sfbr) register. these bits are used in conjunction with the data compare mask field to test for a particular data value. 6.6.2 second dword jump address [31:0] this 32-bit ?eld contains the address of the next instruction to fetch when a jump is taken. once the SYM53C895 fetches the instruction from the address pointed to by these 32 bits, this address is incremented by 4, loaded into the dma scripts pointer (dsp) register and becomes the current instruction pointer. 31 24 23 16 15 8 7 0 dsps (dma scripts pointer save) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
memory move instructions 6-33 6.7 memory move instructions for memory move instructions, bits 5 and 4 (siom and diom) in the dma mode (dmode) register determine whether the source or destination addresses reside in memory or i/o space. by setting these bits appropriately, data may be moved within memory space, within i/o space, or between the two address spaces. the memory move instruction is used to copy the speci?ed number of bytes from the source address to the destination address. allowing the SYM53C895 to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current dma controllers. up to 16 mbytes may be transferred with one instruction. there are two restrictions: both the source and destination addresses must start with the same address alignment (a[1:0]) must be the same). if the source and destination are not aligned, then an illegal instruction interrupt occurs. for the pci cache line size register setting to take effect, the source and destination must be the same distance from a cache line boundary. indirect addresses are not allowed. a burst of data is fetched from the source address, put into the dma fifo and then written out to the destination address. the move continues until the byte count decrements to zero, then another script is fetched from system memory. the dma scripts pointer save (dsps) and data structure address (dsa) registers are additional holding registers used during the memory move. however, the contents of the data structure address (dsa) register are preserved.
6-34 scsi scripts instruction set 6.7.1 first dword it[2:0] instruction type - memory move [31:29] the it bit con?guration (110) de?nes a memory move instruction type. r reserved [28:25] these bits are reserved and must be zero. if any of these bits are set, an illegal instruction interrupt occurs. nf no flush 24 when this bit is set, the SYM53C895 performs a memory move without ?ushing the prefetch unit. when this bit is cleared, the memory move instruction automatically ?ushes the prefetch unit. use the no flush option if the source and destination are not within four instructions of the current memory move instruction. note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. for information on scripts instruction prefetching, see chapter 2, "functional description" . tc[23:0] transfer counter [23:0] the number of bytes to transfer is stored in the lower 24 bits of the ?rst instruction word. 6.7.2 read/write system memory from a script by using the memory move instruction, single or multiple register values are transferred to or from system memory. because the SYM53C895 responds to addresses as de?ned in the base address register zero (i/o) or base address register one (memory) registers, it can be accessed during a memory move operation if the source or destination address decodes to within the chip register space. if this occurs, the register indicated by the lower seven bits of the address is taken as the data source or destination. in this way, register values are 31 29 28 25 24 23 16 15 8 7 0 dcmd (dma command) register dbc (dma byte counter) register it[2:0] r nf tc (transfer counter) [23:0] 1100000xxxxxxxxxxxxxxxxx xxxxxxxx
memory move instructions 6-35 saved to system memory and later restored, and scripts can make decisions based on data values in system memory. the scsi first byte received (sfbr) is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using scripts read/write operations. to load the sfbr with a byte stored in system memory, ?rst move the byte to an intermediate SYM53C895 register (for example, a scratch register), and then to the scsi first byte received (sfbr). the same address alignment restrictions apply to register access operations as to normal memory to memory transfers. 6.7.3 second dword - dsps register [31:0] these bits contain the source address of the memory move. 6.7.4 third dword temp register [31:0] these bits contain the destination address for the memory move. 31 24 23 16 15 8 7 0 dsps (dma scripts pointer save) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 31 24 23 16 15 8 7 0 temp (temporary) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
6-36 scsi scripts instruction set 6.8 load and store instructions the load and store instructions provide a more ef?cient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction. the load and store instructions are represented by two-dword op codes. the ?rst dword contains the dma command (dcmd) and dma byte counter (dbc) register values. the second dword contains the dma scripts pointer save (dsps) value. this is either the actual memory location of where to load/store, or the offset from the data structure address (dsa), depending on the value of bit 28 (dsa relative). a maximum of 4 bytes may be moved with these instructions. the register address and memory address must have the same byte alignment, and the count set such that it does not cross dword boundaries. the memory address may not map back to the chip, excluding ram and rom. if it does, a pci read/write cycle occurs (the data does not actually transfer to/from the chip), and the chip issues an interrupt (illegal instruction detected) immediately following. the siom and diom bits in the dma mode (dmode) register determine whether the destination or source address of the instruction is in memory space or i/o space, as illustrated in the following table. the load/store utilizes the pci commands for i/o read and i/o write to access the i/o space. bit a1 bit a0 number of bytes allowed to load/store 0 0 one, two, three or four 0 1 one, two, or three 1 0 one or two 1 1 one bit source destination siom (load) memory register diom (store) register memory
load and store instructions 6-37 6.8.1 first dword it[2:0] instruction type [31:29] these bits should be 0b111, indicating the load and store instruction. dsa dsa relative 28 when this bit is cleared, the value in the dma scripts pointer save (dsps) is the actual 32-bit memory address used to perform the load/store to/from. when this bit is set, the chip determines the memory address to perform the load/store to/from by adding the 24 bit signed offset value in the dma scripts pointer save (dsps) to the data structure address (dsa). r reserved [27:26] nf no flush (store instruction only) 25 when this bit is set, the SYM53C895 performs a store without ?ushing the prefetch unit. when this bit is cleared, the store instruction automatically ?ushes the prefetch unit. use no flush if the source and destination are not within four instructions of the current store instruction. this bit has no effect on the load instruction. note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. for information on scripts instruction prefetching, see chapter 2, "functional description" . ls load/store 24 when this bit is set, the instruction is a load. when cleared, it is a store. r reserved [23] ra[6:0] register address [22:16] a[6:0] selects the register to load/store to/from within the SYM53C895. 31 29 28 27 26 25 24 23 16 15 8 7 3 2 0 dcmd (dma command) register dbc (dma byte counter) register it[2:0] dsa r nf ls r ra[6:0] r bc 1 1 1 x 0 0 x x 0xxxxxxx0000000000000xxx
6-38 scsi scripts instruction set r reserved [15:3] bc byte count [2:0] this value is the number of bytes to load/store. 6.8.2 second dword memory i/o address/dsa offset [31:0] this is the actual memory location of where to load/store, or the offset from the data structure address (dsa) register value. 6.8.3 third dword temp register [31:0] these bits contain the destination address for the memory move. 31 24 23 16 15 8 7 0 dsps (dma scripts pointer save) register - memory i/o address/dsa offset xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 31 24 23 16 15 8 7 0 temp (temporary) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
symbios SYM53C895 pci to ultra2 scsi i/o processor 7-1 chapter 7 electrical characteristics this chapter speci?es the SYM53C895 electrical and mechanical characteristics. it is divided into the following sections: section 7.1, dc characteristics, page 7-1 section 7.2, 3.3 volt pci dc characteristics, page 7-6 section 7.3, tolerant technology electrical characteristics, page 7-8 section 7.4, ac characteristics, page 7-11 section 7.5, pci and external memory interface timing diagram, page 7-14 section 7.6, scsi timings, page 7-51 7.1 dc characteristics table 7.1 absolute maximum stress ratings 1 1. stresses beyond those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the operating conditions section of the manual is not implied. symbol parameter min max unit test conditions t stg storage temperature - 55 150 cC v dd supply voltage - 0.5 5.0 v C v in input voltage v ss - 0.3 v dd + 0.3 v C i lp 2 2. - 2v 7-2 electrical characteristics 3. scsi pins only table 7.2 operating conditions symbol parameter min max 1 1. conditions that exceed the operating limits may cause the device to function incorrectl unit test conditions v dd supply voltage 3.135 3.465 v C i dd supply current (dynamic) supply current (static) C C 130 1 ma ma C C i dd-scsi lvd pad supply current C 600 ma rbias = 2.2 k w, v dd = 3.3 v t a operating free air 0 70 cC q ja thermal resistance (junction to ambient air) C67 c/w C table 7.3 scsi signals, low voltage differential drivers - sd[15:0]+/ - , sdp[1:0]+/ - , sreq+/ - , sack+/ - , smsg+/ - , sio+/ - , scd+/ - , satn+/ - , sbsy+/ - , ssel+/ - , srst+/ - * symbol parameter 1 1. v cm = 0.7C1.8 v, r l = 0C110 w, r bias = 2.2 k w . positive current is into scsi i/o processor. min max units test conditions i o + source (+) current 7 13 ma asserted state i o - sink ( - ) current - 7 - 13 ma asserted state i o + sink ( - ) current - 3.5 - 6.5 ma negated state i o - source (+) current 3.5 6.5 ma negated state i oz 3-state leakage - 20 20 m a i oz (srst - only) 3-state leakage - 500 - 50 m a
dc characteristics 7-3 figure 7.1 lvd transmitter figure 7.2 lvd receiver table 7.4 scsi signals, low voltage differential receivers - sd[15:0]+/ - , sdp[1:0]+/ - , sreq+/ - , sack+/ - , smsg+/ - , sio+/ - , scd+/ - , satn+ - , sbsy+/ - , ssel+/ - , srst+/ - symbol parameter 1 1. vcm = 0.7 - 1.8 v min max units v i lvd receiver voltage asserting 60 C mv v i lvd receiver voltage negating C - 60 mv + - + v cm i o + i o + r l 2 r l 2 - + - v i 2 v i 2 + v cm - + - - + table 7.5 scsi signal - diffsens symbol parameter min max unit test conditions v ih high voltage differential sense voltage 2.4 v dd + 0.3 v C v s lvd sense voltage 0.7 1.9 v C v il single-ended sense voltage v ss - 0.3 0.5 v C i oz 3-state leakage - 10 10 m aC
7-4 electrical characteristics table 7.6 scsi signals - rbias+/ - symbol parameter min max unit test conditions v in input voltage v dd - 0.2 C v - 125 m a table 7.7 capacitance symbol parameter min max unit test conditions c i input capacitance of input pads C 7 pf C c io input capacitance of i/o pads C15 pfC table 7.8 output signal - mac/_testout symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v - 16 ma v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage - 10 10 m aC table 7.9 input signals - clk 1 , rst/ 1 , idsel, gnt/, sclk/ 1. i pull not possible symbol parameter min max unit test conditions v ih input high voltage 0.5 v dd v5bias(pci) v C v il input low voltage v ss - 0.3 0.3 v dd vC i in input current - 10 10 m aC i pull pull-up current 25 C m a
dc characteristics 7-5 table 7.10 bidirectional signals - ad[31:0], c_be/[3:0], frame/, irdy/, trdy/, devsel/, stop/, perr/, par, req/ irq/, serr/ symbol parameter min max unit test conditions v ih input high voltage 0.5 v dd v5bias(pci) v C v il input low voltage v ss - 0.5 0.3 v dd vC v oh output high voltage 0.9 v dd v dd v - 0.5 m a v ol output low voltage v ss 0.1 v dd v 1.5 m a i oz 3-state leakage - 10 10 m aC i pull pull-up current 25 m a table 7.11 bidirectional signals - gpio0_fetch/, gpio1_master/, gpio2, gpio3, gpio4, mad[7:0] symbol parameter min max unit test conditions v ih input high voltage 2.0 v5bias(mem) v C v il input low voltage v ss - 0.5 0.8 v C v oh output high voltage 2.4 v dd v - 8ma v ol output low voltage v ss 0.4 v 8 ma i oz 3-state leakage - 10 10 m aC table 7.12 bidirectional signals - mas/[1:0], mce/, moe/, mwe/ symbol parameter min max unit test conditions v ih input high voltage 2.0 v5bias (pci or mem) vC v il input low voltage v ss - 0.5 0.8 v C v oh output high voltage 2.4 v dd v - 4ma v ol output low voltage v ss 0.4 v 4 ma i oz 3-state leakage - 10 10 m aC i pull pull-up current 25 C m aC
7-6 electrical characteristics 7.2 3.3 volt pci dc characteristics these characteristics apply whenever a v dd source of 3.3 volts is supplied to the v dd - i pins of the SYM53C895. table 7.13 input signal - big_lit/ symbol parameter min max unit test conditions v ih input high voltage 2.0 v5bias(pci) v C v il input low voltage v ss - 0.5 0.8 v C i in input current - 10 10 m aC i pull pull-up current 25 C m aC table 7.14 bidirectional signals - ad[31:0], c_be[3:0]/, frame/, irdy/, trdy/, devsel/, stop/, perr/, par, bytepar[3:0] symbol parameter min max units test conditions v ih input high voltage 0.5 v dd v dd + 0.5 v C v il input low voltage - 0.5 0.3 v dd v- v oh output high voltage 0.9 v dd Cv - 0.5 ma v ol output low voltage C 0.1 v dd v 1.5 ma i oz 3-state leakage - 10 10 v C table 7.15 input signals - clk, gnt/, idsel, rst/ symbol parameter min max units test conditions v ih input high voltage 0.5 v dd v dd + 0.5 v C v il input low voltage - 0.5 0.3 v dd vC i in input leakage - 10 10 m aC
3.3 volt pci dc characteristics 7-7 table 7.16 output signals - irq/, req/ symbol parameter min max units test conditions v oh output high voltage 0.9 v dd Cv - 0.5 ma v ol output low voltage C 0.1 v dd v 1.5 ma i oz 3-state leakage - 10 10 m aC table 7.17 output signal - serr/ symbol parameter min max units test conditions v ol output low voltage C 0.1 v dd v 1.5 ma i oz 3-state leakage - 10 10 m aC
7-8 electrical characteristics 7.3 tolerant technology electrical characteristics table 7.18 tolerant technology electrical characteristics 1 symbol parameter min max units test conditions v oh 2 output high voltage 2.0 v dd + 0.3 v i oh =7ma v ol output low voltage v ss 0.5 v i ol =48ma v ih input high voltage 2.0 v dd + 0.3 v C v il input low voltage v ss - 0.3 0.8 v referenced to v ss v ik input clamp voltage - 0.66 - 0.77 v v dd = 4.75; i i = - 20 ma v th threshold, high to low 1.0 1.2 v C v tl threshold, low to high 1.4 1.6 v C v th -v tl hysteresis 300 500 mv C i oh 2 output high current 2.5 24 ma v oh = 2.5 v i ol output low current 100 200 ma v ol = 0.5 v i osh 2 short-circuit output high current C 625 ma output driving low, pin shorted to v dd supply 3 i osl short-circuit output low current C 95 ma output driving high, pin shorted to v ss supply i lh input high leakage C 20 m a - 0.5 < v dd < 5.25 v pin = 2.7 v i ll input low leakage C - 20 m a - 0.5 < v dd < 5.25 v pin = 0.5 v r i input resistance 20 C m w scsi pins 4 c p capacitance per pin C 15 pf pqfp t r 2 rise time, 10% to 90% 4.0 18.5 ns figure 7.1 t f fall time, 90% to 10% 4.0 18.5 ns figure 7.1 dv h /dt slew rate, low to high 0.15 0.50 v/ns figure 7.1 dv l /dt slew rate, high to low 0.15 0.50 v/ns figure 7.1
tolerant technology electrical characteristics 7-9 figure 7.3 rise and fall time test conditions figure 7.4 input filtering esd electrostatic discharge 2 C kv mil-std-883c; 3015-7 latch-up 100 C ma C filter delay 20 30 ns figure 7.2 ultra ?lter delay 10 15 ns figure 7.2 ultra2 ?lter delay 5 8 ns figure 7.2 extended ?lter delay 40 60 ns figure 7.2 1. these values are guaranteed by periodic characterization; they are not 100% tested on every device. 2. active negation outputs only: data, parity, sreq/, sack/. 3. single pin only; irreversible damage may occur if sustained for one second. 4. scsi reset pin has 10 k w pull-up resistor. table 7.18 tolerant technology electrical characteristics 1 (cont.) symbol parameter min max units test conditions + - 47 w 2.5 v 20 pf req/ or ack/input * t 1 is the input ?ltering period t 1 v th
7-10 electrical characteristics figure 7.5 hysteresis of scsi receiver figure 7.6 input current as a function of input voltage reviewed logic level 1 0 input voltage (volts) 1.1 1.3 1.5 1.7 +40 +20 0 - 20 - 40 - 4 0 4 8 12 16 - 0.7 v 8.2 v hi-z output active input voltage (volts) input current (milliamperes) 14.4 v
ac characteristics 7-11 figure 7.7 output current as a function of output voltage 7.4 ac characteristics the ac characteristics described in this section apply over the entire range of operating conditions (refer to the dc characteristics section). chip timings are based on simulation at worst case voltage, temperature, and processing. 0 -200 -400 -600 -800 3 01 2 45 output voltage (volts) 100 80 60 40 0 3 01 2 45 output voltage (volts) 20 table 7.19 external clock timing 1 symbol parameter min max units t 1 bus clock cycle time 30 dc ns scsi clock cycle time (sclk) 2 25 60 ns
7-12 electrical characteristics timings were developed with a load capacitance of 50 pf. figure 7.8 external clock timing t 2 clk low time 3 10 C ns sclk low time 3 633ns t 3 clk high time 3 12 C ns sclk high time 3 10 33 ns t 4 clk slew rate 1 C v/ns sclk slew rate 1 C v/ns 1. timings are for an external 40 mhz clock. a quadrupled 40 mhz clock is required for ultra2 scsi operation. 2. this parameter must be met to insure scsi timings are within speci?cation. 3. duty cycle not to exceed 60/40. table 7.19 external clock timing 1 (cont.) symbol parameter min max units clk/sclk 1.4 v t 1 t 3 t 4 t 2
ac characteristics 7-13 figure 7.9 reset input table 7.20 reset input symbol parameter min max units t 1 reset pulse width 10 C t clk t 2 reset deasserted setup to clk high 0Cns t 3 mad setup time to clk high (for con?guring the mad bus only) 20 C ns t 4 mad hold time from clk high (for con?guring the mad bus only) 20 C ns t 1 t 2 t 3 t 4 clk rst/ mad* *when enabled valid data
7-14 electrical characteristics figure 7.10 interrupt output 7.5 pci and external memory interface timing diagram figure 7.11 through figure 7.35 represent signal activity when the SYM53C895 accesses the pci bus. this section includes timing diagrams for access to three groups of external memory con?gurations. the ?rst group applies to systems with memory size of 64 kbytes and above; one byte read or write cycle, and fast or normal roms. the second group applies to systems with memory size of 64 kbytes and above, one-byte read or write cycles, and slow roms. the third group applies to systems with memory size of 64 kbytes or less, one-byte read or write cycles, and normal or fast rom. note: multiple byte accesses to the external memory bus increase the read or write cycle by 11 clocks for each addi- tional byte. table 7.21 interrupt output symbol parameter min max units t 1 clk high to irq/ low 2 11 ns t 2 clk high to irq/ high 2 11 ns t 3 irq/ deassertion time 3 C clks t 1 t 2 t 3 irq/ clk
pci and external memory interface timing diagram 7-15 7.5.1 timing diagrams included in this section 7.5.1.1 target cycles pci con?guration register read pci con?guration register write operating register/scripts ram read operating register/scripts ram write external memory read external memory write 7.5.1.2 initiator cycles op code fetch, nonburst burst op code fetch back-to-back read back-to-back write burst read burst write 7.5.1.3 external memory cycles read cycle, normal/fast memory ( 3 128 kbytes), single-byte access write cycle, normal/fast memory ( 3 128 kbytes), single-byte access read cycle, normal/fast memory ( 3 128 kbytes), multiple-byte access write cycle, normal/fast memory ( 3 128 kbytes), multiple-byte access read cycle, slow memory ( 3 128 kbytes) write cycle, slow memory ( 3 128 kbytes) read cycle, 64 kbytes rom write cycle, 64 kbytes rom
7-16 electrical characteristics figure 7.11 pci con?guration register read table 7.22 con?guration register read timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns data out byte enable t 2 out t 1 t 1 t 3 t 2 t 1 t 1 t 2 t 2 t 3 t 3 t 2 t 1 t 3 t 2 t 1 clk (driven by system) frame/ (driven by master) ad[31:0] (driven by master-addr; 53c895-data) c_be[3:0]/ (driven by master) pa r (driven by master-addr; 53c895-data) irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) idsel (driven by master) t 3 addr in cmd in
pci and external memory interface timing diagram 7-17 figure 7.12 pci con?guration register write table 7.23 con?guration register write timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 t 2 t 1 clk (driven by system) frame/ (driven by master) ad[31:0] (driven by master) c_be[3:0]/ (driven by master) pa r (driven by master) irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) idsel (driven by master) t 1 t 2 t 3 addr in cmd data in byte enable
7-18 electrical characteristics figure 7.13 operating register/scripts ram read table 7.24 operating register/scripts ram read timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns data byte enable cmd t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad[31:0] (driven by master-addr; c_be[3:0]/ (driven by master) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) out t 3 in out t 3 53c895-data) 53c895-data addr in
pci and external memory interface timing diagram 7-19 figure 7.14 operating register/scripts ram write table 7.25 operating register/scripts ram write timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad[31:0] (driven by master) c_be[3:0]/ (driven by master) pa r (driven by master) irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) in t 2 t 1 in t 2 t 1 addr in cmd
7-20 electrical characteristics table 7.26 external memory read timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 4 side signal input setup time 10 C ns t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 160 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0Cns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns
pci and external memory interface timing diagram 7-21 figure 7.15 external memory read clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) ad[31:0] (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) data driven by memory) 1234 56 78910 53c895-data) addr in byte enable 53c895-data) mad (addr driven by 53c895; high order address middle order address low order address mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) t 1 t 2 t 1 t 2 cmd in t 1 t 2 t 1 t 1 t 3 t 13 t 11 t 12 t 15
7-22 electrical characteristics figure 7.15 external memory read (cont.) clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) ad[31:0] (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) data driven by memory) 11 12 13 14 15 16 17 18 19 20 53c895-data) data out 53c895-data) mad (addr driven by 53c895; mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) t 3 t 2 t 2 t 15 21 t 3 out t 3 t 3 data in t 19 t 17 t 14 t 16 receive data
pci and external memory interface timing diagram 7-23 table 7.27 external memory write timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid - 11 ns t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 75 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns
7-24 electrical characteristics figure 7.16 external memory write clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) ad[31:0] (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) 12 3 4 5 6 78 910 53c895-data) 53c895-data) mad (driven by 53c895) high order address middle order address low order address mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 3 t 13 t 11 t 12 t 23 t 20 addr in cmd in
pci and external memory interface timing diagram 7-25 figure 7.16 external memory write (cont.) clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) ad[31:0] (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) 11 12 13 14 15 16 17 18 19 20 53c895-data) 53c895-data) mad (driven by 53c895) mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) t 2 t 2 t 3 21 t 1 t 3 t 3 t 24 t 22 data out t 25 t 26 t 21 t 20 t 23 t 2 data in byte enable in
7-26 electrical characteristics table 7.28 op code fetch, nonburst timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 7 clk high to fetch/ low C 20 ns t 8 clk high to fetch/ high C 20 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
pci and external memory interface timing diagram 7-27 figure 7.17 op code fetch, nonburst t 7 t 9 t 3 t 4 t 1 t 3 t 1 clk (driven by system) gpio0_fetch/ (driven by 53c895) gpio1_master/ (driven by 53c895) req/ (driven by 53c895) pa r (driven by 53c895- irdy/ (driven by 53c895) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 1 t 8 t 6 t 3 ad[31:0] (driven by 53c895- c_be[3:0]/ (driven by 53c895) t 3 cmd t 10 t 1 t 2 gnt/ (driven by arbiter) frame/ (driven by 53c895) t 5 data in addr out data in addr out byte enable cmd byte enable t 3 t 2 t 2 addr; target-data) addr; target-data)
7-28 electrical characteristics table 7.29 burst op code fetch timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 7 clk high to fetch/ low C 20 ns t 8 clk high to fetch/ high C 20 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
pci and external memory interface timing diagram 7-29 figure 7.18 burst op code fetch t 7 t 9 t 3 t 4 t 1 t 3 t 1 clk (driven by system) gpio0_fetch/ (driven by 53c895) gpio1_master/ (driven by 53c895) req/ (driven by 53c895) pa r (driven by 53c895- irdy/ (driven by 53c895) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 1 t 8 t 6 t 3 ad[31:0] (driven by 53c895- c_be[3:0]/ (driven by 53c895) t 3 t 10 t 1 t 2 gnt/ (driven by arbiter) frame/ (driven by 53c895) t 3 t 2 t 2 addr; target-data) addr; target-data) t 5 t 3 t 2 addr out cmd byte enable data in data in out in in
7-30 electrical characteristics table 7.30 back to back read timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
pci and external memory interface timing diagram 7-31 figure 7.19 back-to-back read t 9 t 4 t 1 t 3 t 1 clk (driven by system) gpio0_fetch/ (driven by 53c895) gpio1_master/ (driven by 53c895) req/ (driven by 53c895) pa r (driven by 53c895- irdy/ (driven by 53c895) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 1 t 6 t 3 ad[31:0] (driven by 53c895- c_be[3:0]/ (driven by 53c895) t 1 cmd t 2 t 10 t 1 t 2 gnt/ (driven by arbiter) frame/ (driven by 53c895) t 5 data in addr out data in addr out cmd t 3 t 2 t 2 addr; target-data) addr; target-data) t 3 be be out in out in
7-32 electrical characteristics table 7.31 back to back write timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
pci and external memory interface timing diagram 7-33 figure 7.20 back-to-back write t 9 t 4 t 3 t 1 clk (driven by system) gpio0_fetch/ (driven by 53c895) gpio1_master/ (driven by 53c895) req/ (driven by 53c895) pa r (driven by 53c895) irdy/ (driven by 53c895) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 6 t 3 ad[31:0] (driven by 53c895) c_be[3:0]/ (driven by 53c895) t 3 t 10 gnt/ (driven by arbiter) frame/ (driven by 53c895) t 5 t 3 t 2 t 3 t 3 t 3 cmd be cmd t 3 addr out addr out data out data out be
7-34 electrical characteristics table 7.32 burst read timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
pci and external memory interface timing diagram 7-35 figure 7.21 burst read t 1 t 2 clk (driven by system) gpio0_fetch/ (driven by 53c895) gpio1_master/ (driven by 53c895) req/ (driven by 53c895) pa r (driven by 53c895 irdy/ (driven by 53c895) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad[31:0] (driven by 53c895- c_be[3:0]/ (driven by 53c895) cmd gnt/ (driven by arbiter) frame/ (driven by 53c895) addr out t 2 t 2 addr; target-data) for addr; by target be t 1 data in in for data) be be cmd cmd out in out in in out data in addr out addr out data in t 9 t 10 t 6 t 4 t 5 t 3 t 3 t 2 t 1 t 3 t 3 t 3 t 1
7-36 electrical characteristics table 7.33 burst write timings symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns
pci and external memory interface timing diagram 7-37 figure 7.22 burst write clk (driven by system) gpio0_fetch/ (driven by 53c895) gpio1_master/ (driven by 53c895) req/ (driven by 53c895) pa r (driven by 53c895 irdy/ (driven by 53c895) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad[31:0] (driven by 53c895- c_be[3:0]/ (driven by 53c895) cmd gnt/ (driven by arbiter) frame/ (driven by 53c895) addr; target-data) for addr; by target 1 3 5 7 9 11 13 15 17 19 for data) cmd cmd addr t 9 t 10 t 6 t 4 t 5 t 3 t 3 t 2 t 3 t 3 t 3 out data out addr out addr out data out data out t 3 t 3 be be t 3 be t 2 t 1 t 1 t 2
7-38 electrical characteristics table 7.34 read cycle timings, normal/fast memory ( 3 128 kbytes), single byte access symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 160 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0Cns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns
pci and external memory interface timing diagram 7-39 figure 7.23 read cycle, normal/fast memory ( 3 128 kbytes), single byte access figure 7.23 read cycle, normal/fast memory ( 3 128 kbytes), single byte access (cont.) clk data driven by memory) 12 3 4 5 6 78 910 mad (driven by 53c895; high order address middle order address low order address mas1/ (driven by 53c895) mas0/ (driven by 53c8965) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) t 13 t 11 t 12 t 15 t 14 t 16 clk data driven by memory) 11 12 13 14 15 16 17 18 19 20 mad (driven by 53c895; mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) t 15 21 read data t 14 t 16 valid t 18
7-40 electrical characteristics figure 7.24 normal/fast memory ( 3 128 kbytes), single byte access, write cycle, table 7.35 write cycle timings, normal/fast memory ( 3 128 kbytes), single byte access symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 75 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns clk 12 3 4 5 6 78 910 mad (driven by 53c895) high order address middle address low address mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) t 13 t 11 t 12 t 24 t 25 write data valid t 23 t 20 t 22
pci and external memory interface timing diagram 7-41 figure 7.24 normal/fast memory ( 3 128 kbytes) single byte access write cycle (cont.) clk 11 12 13 14 15 16 17 18 19 20 mad (driven by 53c895) mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) 21 t 24 t 21 valid write data t 22 t 26
7-42 electrical characteristics figure 7.25 normal/fast memory ( 3 128 kbytes), multiple byte access, read cycle clk (driven by system) pa r (driven by 53c895- irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) ad[31:0] (driven by 53c895- c_be[3:0]/ (driven by master) frame/ (driven by master) master-addr; data) master-addr;-data) mad (addr driven by 53c895 mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) 12 345 6789101112131415 addr byte enable data driven by memory) high order address order address middle order address low in cmd in
pci and external memory interface timing diagram 7-43 figure 7.25 normal/fast memory ( 3 128 kbytes) multiple byte access, read cycle (cont.) clk (driven by system) pa r (driven by 53c895- irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) ad[31:0] (driven by 53c895- c_be[3:0]/ (driven by master) frame/ (driven by master) master-addr; data) master-addr;-data) mad (addr driven by 53c895 mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 byte enable data driven by memory) 16 32 33 data out out data in low order address data in
7-44 electrical characteristics figure 7.26 normal/fast memory ( 3 128 kbytes) multiple byte access, write cycle clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) ad[31:0] (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) 53c895-data) 53c895-data) mad (driven by 53c895) mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) 12 345 6789101112131415 byte enable in high order address order address middle order address low data in data out cmd in addr
pci and external memory interface timing diagram 7-45 figure 7.26 normal/fast memory ( 3 128 kbytes) multiple byte access, write cycle (cont.) clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) ad[31:0] (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) 53c895-data) 53c895-data) mad (driven by 53c895 mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 byte enable 16 32 33 low order address data in in data out
7-46 electrical characteristics figure 7.27 read cycle, slow memory ( 3 128 kbytes) table 7.36 read cycle timings, slow memory ( 3 128 kbytes) symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 160 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0C ns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns clk data driven by memory) 11 12 13 14 15 16 17 18 19 20 mad (addr driven by 53c895; mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) t 15 21 read data t 19 t 17 t 14 t 16 valid t 18 22
pci and external memory interface timing diagram 7-47 figure 7.28 write cycle, slow memory ( 3 128 kbytes) table 7.37 write cycle timings, slow memory ( 3 128 kbytes) symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 75 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns clk 12 3 4 5 6 78 910 mad (driven by 53c895) high order address middle address low order address mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) t 13 t 11 t 12 t 24 t 25 write data valid t 23 t 20 t 22
7-48 electrical characteristics figure 7.28 write cycle, slow memory ( 3 128 kbytes) (cont.) clk 11 12 13 14 15 16 17 18 19 20 mad (driven by 53c895) mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) 21 t 24 t 21 valid write data t 22 t 26
pci and external memory interface timing diagram 7-49 figure 7.29 read cycle, 64 kbytes rom table 7.38 read cycle timings, 64 kbytes rom symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 160 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0Cns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns clk 1234 5 6 78910 mad (addr drvn by 53c895; high order address low order address mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) t 13 t 11 t 12 t 15 t 16 11 12 13 14 valid read data t 14 t 18 t 19 t 17 data drvn by mem)
7-50 electrical characteristics figure 7.30 write cycle, 64 kbytes rom table 7.39 write cycle timings, 64 kbytes rom symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 75 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns clk 1234 5 6 78910 mad (driven by 53c895) mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) t 13 t 11 t 12 t 22 11 12 13 t 24 t 21 valid write data t 23 t 25 t 26 t 20 high order address low order address
scsi timings 7-51 7.6 scsi timings figure 7.31 initiator asynchronous send table 7.40 initiator asynchronous send symbol parameter min max units t 1 sack/ asserted from sreq/ asserted 5 C ns t 2 sack/ deasserted from sreq/ deasserted 5 C ns t 3 data setup to sack/ asserted 55 C ns t 4 data hold from sreq/ deasserted 20 C ns valid n valid n + 1 n + 1 n + 1 n n t 1 t 2 t 3 t 4 sreq/ sack/ sd[15:0]/, sdp[1:0]/
7-52 electrical characteristics figure 7.32 initiator asynchronous receive figure 7.33 target asynchronous send table 7.41 initiator asynchronous receive symbol parameter min max units t 1 sack/ asserted from sreq/ asserted 5 C ns t 2 sack/ deasserted from sreq/ deasserted 5 C ns t 3 data setup to sreq/ asserted 0 C ns t 4 data hold from sack/ asserted 0 C ns table 7.42 target asynchronous send symbol parameter min max units t 1 sreq/ deasserted from sack/ asserted 5 C ns t 2 sreq/ asserted from sack/ deasserted 5 C ns t 3 data setup to sreq/ asserted 55 C ns t 4 data hold from sack/ asserted 20 C ns valid n valid n + 1 n + 1 n + 1 n n t 1 t 2 t 3 t 4 sreq/ sack/ sd[15:0]/, sdp[1:0]/ valid n valid n + 1 n + 1 n + 1 n n t 1 t 2 t 3 t 4 sreq/ sack/ sd[15:0]/, sdp[1:0]/
scsi timings 7-53 figure 7.34 target asynchronous receive figure 7.35 initiator and target synchronous transfers table 7.43 target asynchronous receive symbol parameter min max units t 1 sreq/ deasserted from sack/ asserted 5 C ns t 2 sreq/ asserted from sack/ deasserted 5 C ns t 3 data setup to sack/ asserted 0 C ns t 4 data hold from sreq/ deasserted 0 C ns valid n valid n + 1 n + 1 n + 1 n n t 1 t 2 t 3 t 4 sreq/ sack/ sd[15:0]/, sdp[1:0]/ valid n valid n + 1 n + 1 n t 1 t 2 t 3 t 4 sreq/ send data receive data sdp[1:0]/ or sack/ sd[15:0]/, sdp[1:0]/ sd[15:0]/, t 5 t 6 valid n + 1 valid n
7-54 electrical characteristics table 7.44 scsi-1 transfers (single-ended, 5.0 mbytes/s) symbol parameter min max units t 1 send sreq/ or sack/ assertion pulse width 90 C ns t 2 send sreq/ or sack/ deassertion pulse width 90 C ns t 1 receive sreq/ or sack/ assertion pulse width 90 C ns t 2 receive sreq/ or sack/ deassertion pulse width 90 C ns t 3 send data setup to sreq/ or sack/ asserted 55 C ns t 4 send data hold from sreq/ or sack/ asserted 100 C ns t 5 receive data setup to sreq/ or sack/ asserted 0Cns t 6 receive data hold from sreq/ or sack/ asserted 45 C ns table 7.45 scsi-1 transfers (differential, 4.17 mbytes/s) symbol parameter min max units t 1 send sreq/ or sack/ assertion pulse width 96 C ns t 2 send sreq/ or sack/ deassertion pulse width 96 C ns t 1 receive sreq/ or sack/ assertion pulse width 84 C ns t 2 receive sreq/ or sack/deassertion pulse width 84 C ns t 3 send data setup to sreq/ or sack/ asserted 65 C ns
scsi timings 7-55 t 4 send data hold from sreq/ or sack/ asserted 110 C ns t 5 receive data setup to sreq/ or sack/ asserted 0Cns t 6 receive data hold from sreq/ or sack/ asserted 45 C ns table 7.46 scsi-2 fast transfers 10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 40 mhz clock symbol parameter min max units t 1 send sreq/ or sack/ assertion pulse width 35 C ns t 2 send sreq/ or sack/ deassertion pulse width 35 C ns t 1 receive sreq/ or sack/ assertion pulse width 20 C ns t 2 receive sreq/ or sack/ deassertion pulse width 20 C ns t 3 send data setup to sreq/ or sack/ asserted 33 C ns t 4 send data hold from sreq/ or sack/ asserted 45 C ns t 5 receive data setup to sreq/ or sack/ asserted 0Cns t 6 receive data hold from sreq/ or sack/ asserted 10 C ns table 7.45 scsi-1 transfers (differential, 4.17 mbytes/s) (cont.) symbol parameter min max units
7-56 electrical characteristics table 7.47 scsi-2 fast transfers 10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 50 mhz clock 1 symbol parameter 2 min max unit t 1 send sreq/ or sack/ assertion pulse width 35 C ns t 2 send sreq/ or sack/ deassertion pulse width 35 C ns t 1 receive sreq/ or sack/ assertion pulse width 20 C ns t 2 receive sreq/ or sack/ deassertion pulse width 20 C ns t 3 send data setup to sreq/ or sack/ asserted 33 C ns t 4 send data hold from sreq/ or sack/ asserted 40 3 Cns t 5 receive data setup to sreq/ or sack/ asserted 0Cns t 6 receive data hold from sreq/ or sack/ asserted 10 C ns 1. transfer period bits (bits [6:4] in the sxfer register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scntl1) is set. 2. for fast scsi, set the tolerant enable bit (bit 7 in stest3). 3. analysis of system con?guration is recommended due to reduced driver skew margin in differential systems
scsi timings 7-57 table 7.48 ultra scsi single-ended transfers 20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers), quadrupled 40 mhz clock 1 1. transfer period bits (bits [6:4] in the sxfer register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scntl1) is set. symbol parameter 2 2. for fast scsi, set the tolerant enable bit (bit 7 in stest3). during ultra scsi transfers, the value of the extend req/ack filtering bit (stest2, bit 1) has no effect min max unit t 1 send sreq/ or sack/ assertion pulse width 16 C ns t 2 send sreq/ or sack/ deassertion pulse width 16 C ns t 1 receive sreq/ or sack/ assertion pulse width 10 C ns t 2 receive sreq/ or sack/ deassertion pulse width 10 C ns t 3 send data setup to sreq/ or sack/ asserted 12 C ns t 4 send data hold from sreq/ or sack/ asserted 17 C ns t 5 receive data setup to sreq/ or sack/ asserted 0Cns t 6 receive data hold from sreq/ or sack/ asserted 7Cns
7-58 electrical characteristics table 7.49 ultra scsi high voltage differential transfers 20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers), 80 mhz clock 1 symbol parameter 1 1. during ultra scsi transfers, the value of the extend req/ack filtering bit (stest2, bit 1) has no effect. min max unit t 1 send sreq/ or sack/ assertion pulse width 16 C ns t 2 send sreq/ or sack/ deassertion pulse width 16 C ns t 1 receive sreq/ or sack/ assertion pulse width 10 C ns t 2 receive sreq/ or sack/ deassertion pulse width 10 C ns t 3 send data setup to sreq/ or sack/ asserted 16 C ns t 4 send data hold from sreq/ or sack/ asserted 21 C ns t 5 receive data setup to sreq/ or sack/ asserted 0Cns t 6 receive data hold from sreq/ or sack/ asserted 6Cns
scsi timings 7-59 table 7.50 ultra2 scsi transfers 40.0 mbytes/s (8-bit transfers) or 80.0 mbytes/s (16-bit transfers), quadrupled 40 mhz clock 1 1. transfer period bits (bits [6:4] in the sxfer register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scntl1) is set. symbol parameter 2 2. during ultra2 scsi transfers, the value of the extend req/ack filtering bit (stest2, bit 1) has no effect. min max unit t 1 send sreq/ or sack/ assertion pulse width 8 C ns t 2 send sreq/ or sack/ deassertion pulse width 8Cns t 1 receive sreq/ or sack/ assertion pulse width 6Cns t 2 receive sreq/ or sack/ deassertion pulse width 6Cns t 3 send data setup to sreq/ or sack/ asserted 10 C ns t 4 send data hold from sreq/ or sack/ asserted 10 C ns t 5 receive data setup to sreq/ or sack/ asserted 4.5 C ns t 6 receive data hold from sreq/ or sack/ asserted 4.5 C ns
figure 7.36 SYM53C895 pin diagram, 272-ball bga (top view) a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 vss n/c sd2+ sd3+ sd4+ n/c sd5- sd6- sd7- rbias vdd_ bias satn+ sbsy+ sack+ srst+ smsg+ ssel+ ssel- n/c n/c b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 n/c sd1+ sd1- sd2- sd3- sd4- sd5+ sd6+ sd7+ sdp0- n/c satn- sbsy- sack- srst- smsg- n/c n/c n/c n/c c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 sd0- n/c n/c n/c n/c n/c n/c n/c n/c sdp0+ n/c n/c n/c n/c n/c n/c scd- n/c sreq+ sio- d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 sd0+ n/c n/c vss n/c vdd n/c vss n/c n/c vdd n/c vss n/c vdd scd+ vss sreq- sd8+ sd8- e1 e2 e3 e4 e17 e18 e19 e20 sdp1- n/c n/c n/c sio+ n/c sd9+ sd9- f1 f2 f3 f4 f17 f18 f19 f20 sd15+ sd15- sdp1+ vdd vdd n/c sd10+ sd10- g1 g2 g3 g4 g17 g18 g19 g20 sd14+ sd14- n/c n/c n/c n/c sd11+ sd11- h1 h2 h3 h4 h17 h18 h19 h20 sd13+ sd13- n/c vss vss n/c vdda diffsens j1 j2 j3 j4 j9 j10 j11 j12 j17 j18 j19 j20 lvdsmode (test) sd12+ sd12- n/c vss vss vss vss n/c vssa test_ hsc/ sclk k1 k2 k3 k4 k9 k10 k11 k12 k17 k18 k19 k20 test testin n/c vdd vss vss vss vss n/c n/c mac/_ testout mad0 l1 l2 l3 l4 l9 l10 l11 l12 l17 l18 l19 l20 test test test n/c vss vss vss vss vdd n/c mad2 mad1 m1 m2 m3 m4 m9 m10 m11 m12 m17 m18 m19 m20 mas1/ mas0/ vss_ core n/c vss vss vss vss n/c mad5 mad4 mad3 n1 n2 n3 n4 n17 n18 n19 n20 vss_ core2 mwe/ moe/ vss vss vss_ core mad7 mad6 p1 p2 p3 p4 p17 p18 p19 p20 vdd_ core vdd_ core big_lit/ n/c vdd_ core gpio3 gpio4 vss_ core r1 r2 r3 r4 r17 r18 r19 r20 mce/ rst/ n/c vdd vdd gpio_ master/ vdd_ core gpio2 t1 t2 t3 t4 t17 t18 t19 t20 clk gnt/ n/c n/c n/c n/c gpio0_ fetch/ v5bias (mem) u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 v14 u15 u16 u17 u18 u19 u20 req/ ad31 n/c vss n/c vdd n/c vss c_be2/ vdd serr/ n/c vss n/c vdd n/c vss ad1 n/c irq/ v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 v20 ad30 ad29 ad27 n/c ad25 idsel ad21 ad18 frame/ n/c perr/ ad15 ad12 n/c n/c n/c ad4 ad2 n/c ad0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15 w16 w17 w18 w19 w20 ad28 n/c n/c n/c ad24 ad23 ad20 ad17 irdy/ trdy/ stop/ c_be1/ ad13 ad10 ad8 n/c ad6 v5bias (pci) n/c n/c y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 n/c n/c ad26 v5bias (pci) c_be3/ ad22 ad19 ad16 n/c devsel/ n/c par ad14 ad11 ad9 c_be0/ ad7 ad5 ad3 n/c
scsi timings 7-61 table 7.51 bga position and signal name alphabetically d17 vss d4 vss d8 vss h10 vss h11 vss h12 vss h13 vss h17 vss h4 vss h8 vss h9 vss j10 vss j11 vss j12 vss j13 vss j8 vss j9 vss k10 vss k11 vss k12 vss k13 vss k8 vss k9 vss l10 vss l11 vss l12 vss l13 vss l8 vss l9 vss m10 vss m11 vss m12 vss m13 vss m8 vss m9 vss n10 vss n11 vss n12 vss n13 vss n17 vss n4 vss n8 vss n9 vss u13 vss u17 vss u4 vss u8 vss j18 vssa m3 vsscore n18 vsscore p20 vsscore n1 vsscore2 bga # signal bga # signal v20 ad0 u18 ad1 v18 ad2 y19 ad3 v17 ad4 y18 ad5 w17 ad6 y17 ad7 w15 ad8 y15 ad9 w14 ad10 y14 ad11 v13 ad12 w13 ad13 y13 ad14 v12 ad15 y8 ad16 w8 ad17 v8 ad18 y7 ad19 w7 ad20 v7 ad21 y6 ad22 w6 ad23 w5 ad24 v5 ad25 y3 ad26 v3 ad27 w1 ad28 v2 ad29 v1 ad30 u2 ad31 p3 big_lit/ y16 c_be0/ w12 c_be1/ u9 c_be2/ y5 c_be3/ t1 clk y10 devsel/ h20 diffsens v9 frame/ t2 gnt/ t19 gpio0_fetch/ r18 gpio1_master/ r20 gpio2 p18 gpio3 p19 gpio4 v6 idsel w9 irdy/ u20 irq/ j1 lvdsmode(test) k19 mac/_testout k20 mad0 l20 mad1 l19 mad2 m20 mad3 m19 mad4 m18 mad5 n20 mad6 n19 mad7 m2 mas0/ m1 mas1/ r1 mce/ n3 moe/ n2 mwe/ a19 n/c a2 n/c a20 n/c a6 n/c b1 n/c b11 n/c b17 n/c b18 n/c b19 n/c b20 n/c c11 n/c c12 n/c c13 n/c c14 n/c c15 n/c c16 n/c c18 n/c c2 n/c c3 n/c c4 n/c c5 n/c c6 n/c c7 n/c c8 n/c c9 n/c d10 n/c d12 n/c d14 n/c d2 n/c d3 n/c d5 n/c d7 n/c d9 n/c e18 n/c e2 n/c e3 n/c e4 n/c f18 n/c g17 n/c g18 n/c g3 n/c g4 n/c h18 n/c h3 n/c j17 n/c j4 n/c k17 n/c k18 n/c k3 n/c l18 n/c l4 n/c m17 n/c m4 n/c p4 n/c r3 n/c t17 n/c t18 n/c t3 n/c t4 n/c u12 n/c u14 n/c u16 n/c u19 n/c u3 n/c u5 n/c u7 n/c v10 n/c v14 n/c v15 n/c v16 n/c v19 n/c v4 n/c w16 n/c w19 n/c w2 n/c w20 n/c w3 n/c w4 n/c y1 n/c y11 n/c y2 n/c y20 n/c y9 n/c y12 par v11 perr/ a10 rbias u1 req/ r2 rst/ b14 sack- a14 sack+ b12 satn - a12 satn+ b13 sbsy - a13 sbsy+ c17 scd - d16 scd+ j20 sclk c1 sd0 - b3 sd1 - b4 sd2 - b5 sd3 - b6 sd4 - a7 sd5 - a8 sd6 - a9 sd7 - d20 sd8 - e20 sd9 - f20 sd10 - g20 sd11 - j3 sd12 - h2 sd13 - g2 sd14 - f2 sd15 - d1 sd0+ b2 sd1+ a3 sd2+ a4 sd3+ a5 sd4+ b7 sd5+ b8 sd6+ b9 sd7+ d19 sd8+ e19 sd9+ f19 sd10+ g19 sd11+ j2 sd12+ h1 sd13+ g1 sd14+ f1 sd15+ b10 sdp0 - e1 sdp1 - c10 sdp0+ f3 sdp1+ u11 serr/ c20 sio - e17 sio+ b16 smsg - a16 smsg+ d18 sreq - c19 sreq+ b15 srst - a15 srst+ a18 ssel - a17 ssel+ w11 stop/ k1 test l1 test l2 test l3 test j19 test_hsc/ k2 testin w10 trdy/ t20 v5bias(mem) w18 v5bias(pci) y4 v5bias(pci) d11 vdd d15 vdd d6 vdd f17 vdd f4 vdd k4 vdd l17 vdd r17 vdd r4 vdd u10 vdd u15 vdd u6 vdd a11 vdd_rbias h19 vdda p1 vddcore p17 vddcore p2 vddcore r19 vddcore a1 vss d13 vss bga # signal bga # signal bga # signal 1. nc pins are not connected.
7-62 electrical characteristics table 7.52 bga position numerically and signal name v9 frame/ v10 n/c v11 perr/ v12 ad15 v13 ad12 v14 n/c v15 n/c v16 n/c v17 ad4 v18 ad2 v19 n/c v20 ad0 w1 ad28 w2 n/c w3 n/c w4 n/c w5 ad24 w6 ad23 w7 ad20 w8 ad17 w9 irdy/ w10 trdy/ w11 stop/ w12 c_be1/ w13 ad13 w14 ad10 w15 ad8 w16 n/c w17 ad6 w18 v5bias(pci) w19 n/c w20 n/c y1 n/c y2 n/c y3 ad26 y4 v5bias(pci) y5 c_be3/ y6 ad22 y7 ad19 y8 ad16 y9 n/c y10 devsel/ y11 n/c y12 par y13 ad14 y14 ad11 y15 ad9 y16 c_be0/ y17 ad7 y18 ad5 y19 ad3 y20 n/c bga # signal bga # signal a1 vss a2 n/c a3 sd2+ a4 sd3+ a5 sd4+ a6 n/c a7 sd5 - a8 sd6 - a9 sd7 - a10 rbias a11 vdd_rbias a12 satn+ a13 sbsy+ a14 sack+ a15 srst+ a16 smsg+ a17 ssel+ a18 ssel - a19 n/c a20 n/c b1 n/c b2 sd1+ b3 sd1 - b4 sd2 - b5 sd3 - b6 sd4 - b7 sd5+ b8 sd6+ b9 sd7+ b10 sdp0 - b11 n/c b12 satn - b13 sbsy - b14 sack - b15 srst - b16 smsg - b17 n/c b18 n/c b19 n/c b20 n/c c1 sd0 - c2 n/c c3 n/c c4 n/c c5 n/c c6 n/c c7 n/c c8 n/c c9 n/c c10 sdp0+ c11 n/c c12 n/c c13 n/c c14 n/c c15 n/c c16 n/c c17 scd - c18 n/c c19 sreq+ c20 sio - d1 sd0+ d2 n/c d3 n/c d4 vss d5 n/c d6 vdd d7 n/c d8 vss d9 n/c d10 n/c d11 vdd d12 n/c d13 vss d14 n/c d15 vdd d16 scd+ d17 vss d18 sreq - d19 sd8+ d20 sd8 - e1 sdp1 - e2 n/c e3 n/c e4 n/c e17 sio+ e18 n/c e19 sd9+ e20 sd9 - f1 sd15+ f2 sd15 - f3 sdp1+ f4 vdd f17 vdd f18 n/c f19 sd10+ f20 sd10 - g1 sd14+ g2 sd14 - g3 n/c g4 n/c g17 n/c g18 n/c g19 sd11+ g20 sd11 - h1 sd13+ h2 sd13 - h3 n/c h4 vss h8 vss h9 vss h10 vss h11 vss h12 vss h13 vss h17 vss h18 n/c h19 vdda h20 diffsens j1 lvdsmode(test) j2 sd12+ j3 sd12 - j4 n/c j8 vss j9 vss j10 vss j11 vss j12 vss j13 vss j17 n/c j18 vssa j19 test_hsc/ j20 sclk k1 test k2 testin k3 n/c k4 vdd k8 vss k9 vss k10 vss k11 vss k12 vss k13 vss k17 n/c k18 n/c k19 mac/_testout k20 mad0 l1 test l2 test l3 test l4 n/c l8 vss l9 vss l10 vss l11 vss l12 vss l13 vss l17 vdd l18 n/c l19 mad2 l20 mad1 m1 mas1/ m2 mas0/ m3 vsscore m4 n/c m8 vss m9 vss m10 vss m11 vss m12 vss m13 vss m17 n/c m18 mad5 m19 mad4 m20 mad3 n1 vsscore2 n2 mwe/ n3 moe/ n4 vss n8 vss n9 vss n10 vss n11 vss n12 vss n13 vss n17 vss n18 vsscore n19 mad7 n20 mad6 p1 vddcore p2 vddcore p3 big_lit/ p4 n/c p17 vddcore p18 gpio3 p19 gpio4 p20 vsscore r1 mce/ r2 rst/ r3 n/c r4 vdd r17 vdd r18 gpio1_master/ r19 vddcore r20 gpio2 t1 clk t2 gnt/ t3 n/c t4 n/c t17 n/c t18 n/c t19 gpio0_fetchn t20 v5bias(mem) u1 req/ u2 ad31 u3 n/c u4 vss u5 n/c u6 vdd u7 n/c u8 vss u9 c_be2/ u10 vdd u11 serr/ u12 n/c u13 vss u14 n/c u15 vdd u16 n/c u17 vss u18 ad1 u19 n/c u20 irq/ v1 ad30 v2 ad29 v3 ad27 v4 n/c v5 ad25 v6 idsel v7 ad21 v8 ad18 bga # signal bga # signal bga # signal 1. nc pins are not connected.
scsi timings 7-63 figure 7.37 SYM53C895 pin diagram, 208-pin qfp nc ad26 ad25 vss-pci ad22 ad19 ad17 vss-pci irdy/ devsel/ stop/ perr/ ad14 ad12 ad11 ad10 vss-pci ad8 c_be0/ vdd-pci 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 36 37 38 39 40 42 44 46 48 50 ad21 ad20 vss-pci ad15 ad7 ad6 ad4 v5bias(pci) nc 52 ad2 SYM53C895 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 41 43 45 47 49 51 vdd-pci v5bias(pci) c_be3/ ad23 vdd-pci ad18 frame/ vdd-pci vdd-pci pa r c_be1/ vdd-pci ad24 idsel ad16 c_be2/ trdy/ serr/ ad13 ad9 ad5 ad3 nc nc nc sd1- sd3+ sd4- sd5- vss-scsi sd7- sdp0- rbias+ rbias- sbsy- vss-scsi srst+ srst- smsg- vdd-scsi ssel+ scd- 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 121 120 119 118 117 115 113 111 109 107 sd3- sd4+ satn- sbsy+ ssel- scd+ nc nc nc 105 nc 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 116 114 112 110 108 106 nc nc sd1+ sd2- vdd-scsi sd5+ sd7+ vdd-scsi vss-scsi satn+ vdd-scsi sack- vss-scsi sd2+ sd6+ sd6- sdp0+ vss-scsi sack+ smsg+ vss-scsi nc nc nc ad1 vdd-pci gpio1_master/ gpio4 mad7 mad6 mad3 mad0 mac/_testout sclk vdd-scsi sd10- sd10+ vss-scsi sd9+ sd8- sd8+ sio+ vdd-core gpio3 vss-a vdd-a vdd-scsi sio- sreq+ nc nc nc nc vss-pci irq/ v5bias(mem) gpio2 vss-core vdd-io mad2 vss-io test diffsens sd11+ ad0 gpico_fetch/ mad5 mad4 mad1 vdd-io sd11- sd9- sreq- nc nc nc nc vdd-scsi sd15- sd14+ sd13+ vdd-scsi testin test test vdd-io vdd-core vss-pci rst/ clk vdd-pci req/ ad31 ad29 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 192 193 194 195 196 198 200 202 204 206 sd15+ sd14- vss-core moe/ vss-pci ad30 ad27 nc nc 208 nc 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 197 199 201 203 205 207 nc nc sd0+ sdp1+ vss-scsi sd13- test vss-io test mas0/ mwe/ big_lit/ sd0- sdp1- sd12- sd12+ test mas1/ mce/ gnt/ ad28 nc 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 88 89 90 91 92 94 96 98 100 102 104 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 93 95 97 99 101 103 1. the decoupling capacitor arrangement shown above is recommended to maximize the bene?ts of the internal split ground system. capacitor values between 0.01 and 0.1 m f should provide adequate noise isolation. because of the number of high current drivers on the SYM53C895, a multilayer pc board with power and ground planes is required. 2. a 2.2 k w resistor is required between rbias+ and rbias - pins. rbias - must be connected to 3.3 v as well. 208-pin quad flat pack
7-64 electrical characteristics table 7.53 signal name by pin number qfp vdd-scsi 174 sd12- 175 sd12+ 176 test 177 testin 178 vss-io 179 test 180 test 181 test 182 test 183 vdd-io 184 mas1/ 185 mas0 186 vss-core 187 mwe/ 188 moe/ 189 vdd-core 190 mce/ 191 bit_lit 192 vss-pci 193 rst/ 194 clk 195 gnt/ 196 vdd-pci 197 req/ 198 ad31 199 vss-pci 200 ad30 201 ad29 202 ad28 203 ad27 204 nc 205 nc 206 nc 207 nc 208 signal pin signal pin nc 1 vdd-pci 2 ad26 3 v5bias(pci) 4 ad25 5 ad24 6 c_bd3/ 7 vss-pci 8 idsel 9 ad23 10 ad22 11 ad21 12 vdd-pci 13 ad20 14 ad19 15 ad18 16 ad17 17 vss-pci 18 ad16 19 c_be2/ 20 frame/ 21 irdy/ 22 vdd-pci 23 trdy/ 24 devsel/ 25 vdd-pci 26 stop/ 27 perr/ 28 serr/ 29 pa r 3 0 vss-pci 31 c_be1/ 32 ad15 33 ad14 34 ad13 35 vdd-pci 36 ad12 37 ad11 38 ad10 39 ad9 40 vss-pci 41 ad8 42 c_be0/ 43 ad7 44 ad6 45 vdd-pci 46 ad5 47 ad4 48 v5bias(pci) 49 ad3 50 ad2 51 nc 52 nc 53 nc 54 nc 55 vss-pci 56 ad1 57 ad0 58 ir$q/ 59 vdd-pci 60 gpic0_fetch 61 v5bias(mem) 62 gpio1_master 63 vdd-core 64 gpio2 65 gpio3 66 gpio4 67 vss-core 68 mad7 69 mad6 70 mad5 71 mad4 72 vdd-io 73 mad3 74 mad2 75 mad1 76 mad0 77 vss-io 78 mac/_testout 79 sclk 80 vdd-io 81 test 82 vss-a 83 diffsens 84 vdd-a 85 vdd-scsi 86 sd11 - 87 sd11+ 88 sd10- 89 sd10+ 90 vss-scsi 91 sd9- 92 sd9+ 93 sd8- 94 sd8+ 95 vdd-scsi 96 sio- 97 sio+ 98 sreq- 99 sreq+ 100 nc 101 nc 102 nc 103 nc 104 nc 105 nc 106 nc 107 nc 108 nc 109 vss-scsi 110 scd- 111 scd+ 112 ssel- 113 ssel+ 114 vdd-scsi 115 smsg- 116 smsg+ 117 srst- 118 srst+ 119 vss-scsi 120 sack- 121 sack+ 122 sbsy- 123 sbsy+ 124 vdd-scsi 125 satn- 126 satn+ 127 vss-scsi 128 rbias- 129 rbias+ 130 vss-scsi 131 sdp0- 132 sdp0+ 133 vdd-scsi 134 sd7- 135 sd7+ 136 sd6- 137 sd6+ 138 vss-scsi 139 sd5- 140 sd5+ 141 sd4- 142 sd4+ 143 vdd-scsi 144 sd3- 145 sd3+ 146 sd2- 147 sd2+ 148 sd1- 149 sd1+ 150 vss-scsi 151 nc 153 nc 154 nc 155 nc 156 nc 157 nc 158 nc 159 nc 160 nc 161 sd0- 162 sd0+ 163 vdd-scsi 164 sdp1- 165 sdp1+ 166 sd15- 167 sd15+ 168 vss-scsi 169 sd14- 170 sd14+ 171 sd13- 172 sd13+ 173 signal pin signal pin signal pin 1. nc pins are not connected.
scsi timings 7-65 table 7.54 alphabetical signal name and pin number qfp vdd-pci 13 vdd-pci 23 vdd-pci 26 vdd-pci 36 vdd-pci 46 vdd-pci 60 vdd-pci 197 vdd-scsi 86 vdd-scsi 96 vdd-scsi 115 vdd-scsi 125 vdd-scsi 134 vdd-scsi 144 vdd-scsi 164 vdd-scsi 174 vss-a 83 vss-core 68 vss-core 187 vss-io 78 vss-io 179 vss-pci 8 vss-pci 18 vss-pci 31 vss-pci 41 vss-pci 56 vss-pci 193 vss-pci 200 vss-scsi 91 vss-scsi 110 vss-scsi 120 vss-scsi 128 vss-scsi 131 vss-scsi 139 vss-scsi 151 vss-scsi 169 signal pin signal pin ad0 58 ad2 51 ad3 50 ad1 57 ad4 48 ad5 47 ad6 45 ad7 44 ad8 42 ad9 40 ad10 39 ad11 38 ad12 37 ad13 35 ad14 34 ad15 33 ad16 19 ad17 17 ad18 16 ad19 15 ad20 14 ad21 12 ad22 11 ad23 10 ad24 6 ad25 5 ad26 3 ad27 204 ad28 203 ad29 202 ad30 201 ad31 199 bit_lit 192 c_bd3/ 7 c_be0/ 43 c_be1/ 32 c_be2/ 20 clk 195 devsel/ 25 diffsens 84 frame/ 21 gnt/ 196 gpic0_fetch 61 gpio1_master 63 gpio2 65 gpio3 66 gpio4 67 idsel 9 ir$q/ 59 irdy/ 22 mac/_testout 79 mad0 77 mad1 76 mad2 75 mad3 74 mad4 72 mad5 71 mad6 70 mad7 69 mas0 186 mas1/ 185 mce/ 191 moe/ 189 mwe/ 188 nc 1 nc 52 nc 53 nc 54 nc 55 nc 101 nc 102 nc 103 nc 104 nc 105 nc 106 nc 107 nc 108 nc 109 nc 153 nc 154 nc 155 nc 156 nc 157 nc 158 nc 159 nc 160 nc 161 nc 205 nc 206 nc 207 nc 208 pa r 3 0 perr/ 28 rbias+ 130 rbias- 129 req/ 198 rst/ 194 sack+ 122 sack- 121 satn+ 127 satn- 126 sbsy+ 124 sbsy- 123 scd+ 112 scd- 111 sclk 80 sd0+ 163 sd0- 162 sd1+ 150 sd1- 149 sd10+ 90 sd10- 89 sd11+ 88 sd11 - 87 sd12+ 176 sd12- 175 sd13+ 173 sd13- 172 sd14+ 171 sd14- 170 sd15+ 168 sd15- 167 sd2+ 148 sd2- 147 sd3+ 146 sd3- 145 sd4+ 143 sd4- 142 sd5+ 141 sd5- 140 sd6+ 138 sd6- 137 sd7+ 136 sd7- 135 sd8+ 95 sd8- 94 sd9+ 93 sd9- 92 sdp0+ 133 sdp0- 132 sdp1+ 166 sdp1- 165 serr/ 29 sio+ 98 sio- 97 smsg+ 117 smsg- 116 sreq+ 100 sreq- 99 srst+ 119 srst- 118 ssel+ 114 ssel- 113 stop/ 27 test 82 test 177 test 180 test 181 test 182 test 183 testin 178 trdy/ 24 v5bias(mem) 62 v5bias(pci) 4 v5bias(pci) 49 vdd-a 85 vdd-core 64 vdd-core 190 vdd-io 73 vdd-io 81 vdd-io 184 vdd-pci 2 signal pin signal pin signal pin 1. nc pins are not connected.
7-66 electrical characteristics figure 7.38 SYM53C895 mechanical drawing, 208-pin qfp impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code p9.
scsi timings 7-67 figure 7.38 SYM53C895 mechanical drawing, 208-pin qfp (cont.) impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code p9.
7-68 electrical characteristics figure 7.39 SYM53C895 mechanical drawing, 272 bga impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code v5.
SYM53C895 pci to ultra2 scsi i/o processor a-1 appendix a register summary table a.1 sym53c896 register map register name address read/write page pci registers vendor id 0x00C0x01 read only 5-3 device id 0x02C0x03 read only 5-3 command 0x04C0x05 read/write 5-3 status 0x06C0x07 read/write 5-5 revision id (rev id) 0x08 read only 5-6 class code 0x09C0x0b read only 5-7 cache line size 0x0c read/write 5-7 latency timer 0x0d read/write 5-8 header type 0x0e read only 5-8 base address register zero (i/o) 0x10C0x13 read/write 5-9 base address one (memory) 0x14C0x17 read/write 5-9 ram base address 0x18C0x1b read/write 5-10 subsystem vendor id 0x2cC0x2d read only 5-10 subsystem id 0x2eC0x2f read only 5-11 expansion rom base address 0x30C0x33 read/write 5-12 interrupt line 0x3c read/write 5-13 interrupt pin 0x3d read only 5-13 min_gnt 0x3e read only 5-14
a-2 register summary max_lat 0x3f read only 5-14 scsi registers scsi control zero (scntl0) 0x00 read/write 5-17 scsi control one (scntl1) 0x01 read/write 5-20 scsi control two (scntl2) 0x02 read/write 5-23 scsi contr0l three (scntl3) 0x03 read/write 5-25 scsi chip id (scid) 0x04 read/write 5-28 scsi transfer (sxfer) 0x05 read/write 5-29 scsi destination id (sdid) 0x06 read/write 5-33 general purpose (gpreg) 0x07 read/write 5-34 scsi first byte received (sfbr) 0x08 read/write 5-35 scsi output control latch (socl) 0x09 read /write 5-36 scsi selector id (ssid) 0x0a read only 5-36 scsi bus control lines (sbcl) 0x0b read only 5-37 dma status (dstat) 0x0c read only 5-38 scsi status zero (sstat0) 0x0d read only 5-40 scsi status one (sstat1) 0x0e read only 5-42 scsi status two (sstat2) 0x0f read only 5-44 data structure address (dsa) 0x10C0x13 read/write 5-46 interrupt status (istat) 0x14 read/write 5-46 chip test zero (ctest0) 0x18 read/write 5-49 chip test one (ctest1) 0x19 read only 5-50 chip test two (ctest2) 0x1a read/write 5-50 chip test three (ctest3) 0x1b read/write 5-52 temporary (temp) 0x1cC0x1f read/write 5-53 table a.1 sym53c896 register map (cont.) register name address read/write page
a-3 dma fifo (dfifo) 0x20 (a0) read only 5-53 chip test four (ctest4) 0x21 read/write 5-54 chip test five (ctest5) 0x22 read/write 5-56 chip test six (ctest6) 0x23 read/write 5-57 dma byte counter (dbc) 0x24C0x26 read/write 5-58 dma command (dcmd) 0x27 read/write 5-58 dma next address (dnad) 0x28C0x2b read/write 5-59 dma scripts pointer (dsp) 0x2cC0x2f read/write 5-59 dma scripts pointer save (dsps) 0x30C0x33 read/write 5-59 scratch register a (scratch a) 0x34C0x37 read/write 5-60 dma mode (dmode) 0x38 read/write 5-60 dma interrupt enable (dien) 0x39 read/write 5-63 scratch byte register (sbr) 0x3a read/write 5-64 dma control (dcntl) 0x3b read/write 5-64 adder sum output (adder) 0x3cC0x3f read only 5-66 scsi interrupt enable zero (sien0) 0x40 read/write 5-66 scsi interrupt enable one (sien1) 0x41 read/write 5-68 scsi interrupt status zero (sist0) 0x42 read only 5-69 scsi interrupt status one (sist1) 0x43 read only 5-72 scsi longitudinal parity (slpar) 0x44 read/write 5-73 scsi wide residue (swide) 0x45 read only 5-74 memory access control (macntl) 0x46 read/write 5-74 general purpose pin control (gpcntl) 0x47 read/write 5-75 scsi timer zero (stime0) 0x48 read/write 5-76 scsi timer one (stime1) 0x49 read/write 5-77 table a.1 sym53c896 register map (cont.) register name address read/write page
a-4 register summary response id zero (respid0) 0x4a read/write 5-80 response id one (respid1) 0x4b read/write 5-80 scsi test zero (stest0) 0x4c read only 5-80 scsi test one (stest1) 0x4d read/write 5-82 scsi test two (stest2) 0x4e (0xce) read/write 5-83 scsi test three (stest3) 0x4f (0xcf) read/write 5-85 scsi input data latch (sidl) 0x50C0x51 (0xd0C0xd1 read only 5-88 scsi test 4 (stest4) 0x52 (0xd2) read only 5-88 scsi output data latch (sodl) 0x54C0x55 (0xd4C0xd5) read/write 5-89 scsi bus data lines (sbdl) 0x58C0x59 (0xd8C0xd9) read only 5-89 scratch register b (scratchb) 0x5cC0x5f (0xdcC0xdf) read/write 5-90 scratch registers c-j (scratchcCscratchj) 0x60C0x7f (0xe0C0xff) read/write 5-90 table a.1 sym53c896 register map (cont.) register name address read/write page
SYM53C895 pci to ultra2 scsi i/o processor b-1 appendix b external memory interface diagram examples figure b.1 16 kbytes interface with 200 ns memory SYM53C895 27c128 moe/ mce/ oe ce mad[7:]0 bus d[7:0] mad0 4.7 k v dd a[7:0] a[13:8] mas0/ mas1/ d[5:0] ck q[5:0] oe hct374 note: mad[3:0] pulled low internally. 8 6 6 mad bus sense logic enabled for 16 kbytes of slow memory (200 ns device @ 33 mhz). q[7:0] oe hct374 d[7:0] 8 ck
b-2 external memory interface diagram examples figure b.2 64 kbytes interface with 200 ns memory SYM53C895 27c512-15/ moe/ mce/ oe ce mad[7:0] bus d[7:0] mad0 mad1 mad2 mad3 4.7 k 4.7 k 4.7 k 4.7 k v ss a[7:0] a[13:8] 8 6 mas0/ mas1/ d0 d7 ck q0 q7 oe hct374 d0 d5 ck q0 q5 oe hct374 mad bus sense logic enabled for 64 kbytes of slow memory (200 ns device @ 33 mhz). gpio4 mwe/ + 12 v vpp control vpp optoinal C for flash memory only not required for eeproms we 4.7 k mad0 4.7 k mad2 v dd 28f512-15/ socket
b-3 figure b.3 256 kbytes interface with 150 ns memory SYM53C895 27c020-15/ moe/ mce/ oe ce mad[7:0] bus d[7:0] mad0 mad1 4.7 k 4.7 k v ss a(7:0] a[13:8] 8 8 mas0/ mas1/ d0 d7 ck q0 q7 oe hct374 d0 d5 ck q0 q5 oe hct374 mad bus sense logic enabled for 256 kbytes for fast memory (150 ns device @ 33 mhz). gpio4 mwe/ + 12 v vpp control vpp optoinal C for flash memory only not required for eeproms we 4.7 k mad0 4.7 k mad2 v dd 28f020-15/ socket mad[7:0] bus 8 d0 d1 ck q0 q1 e hct374 the hct374s may be replaced with hct377s.
draft 6/8/99 b-4 external memory interface diagram examples rev. letter copyright ? 1997, 1998 by lsi logic corporation. all rights reserved. figure b.4 512 kbytes interface with 150 ns memory moe/ oe gpio4 mwe/ + 12 v vpp control vpp optoinal C for flash memory only not required for eeproms we mad0 mad1 4.7 k 4.7 k v ss SYM53C895 4.7 k mad0 4.7 k mad2 v dd mas0/ mas1/ mce/ mad[7:0] bus d[7:0] a[7:0] a[13:8] 8 8 mad[7:0] bus 3 d0 d7 a0 a16 oe we d0 d7 a0 a16 oe we d0 d7 a0 a16 oe we d0 d7 a0 a16 a16 ce ce ce ce d0 d7 ck q0 q7 oe hct374 d0 d7 ck q0 q7 oe hct374 d0 d2 ck q0 q2 hct374 e a b gb y0 y1 y2 y3 hct139 mad bus sense logic enabled for 512 kbytes of slow memory (150 ns devices, additional time required for hct139 @ 33 mhz). the hct374s may be replaced with hct377s.
SYM53C895 pci to ultra2 scsi i/o processor c-1 appendix c circuit board layout issues higher data transfer rates, such as ultra2 scsi, make good printed circuit board (pcb) layout practices more critical than ever. some of the layout design criteria that need to be considered are separation of low voltage differential (lvd) and ttl/cmos signals, routing of the differential pairs, trace impedance, stub lengths, decoupling power supplies and the dielectric constant of the board material. when certain pcb layout guidelines are not followed, various signal degradation effects can result. impedance mismatches cause re?ections. crosstalk, dielectric loss, skin effects, dispersion loss and reduction of noise margin are some other unwanted by-products of poor pcb layout practices. note: this information was originally published in symbios system engineering notes 893 (pcb layout for SYM53C895) and 898 (analog power filtering for SYM53C895). this appendix contains these topics: section c.1, signal separation, page c-2 section c.2, routing signal lines, page c-2 section c.3, impedance matching, page c-2 section c.4, termination and stub length, page c-2 section c.5, decoupling, page c-3 section c.6, dielectric, page c-3 section c.7, considerations speci?c to the SYM53C895, page c-3
c-2 circuit board layout issues c.1 signal separation avoid crosstalk problems by providing a good separation between lvd and ttl/cmos signals. crosstalk is proportional to dv/dt. ttl/cmos signals have larger voltage swings than lvd and can effect them if lines are running in close proximity. the best means of separation is to provide a ground trace between the two types of signals. another means of keeping the two kinds of signals apart is to place them on separate layers. if lvd and ttl/cmos signals need to be on the same layer, they should be separated by as much distance as possible. c.2 routing signal lines routing of differential lines is an important factor in maintaining signal integrity. differentially paired traces must be kept equidistant. each line should be kept as parallel as possible to its counterpart. to avoid skew issues, the two lines should be exactly the same in length. abiding by these rules ensures that the rejection of common mode noise, inherent to differentially paired signals, remains intact. another consideration in laying out these traces is to avoid sharp orthogonal turns. this type of turn needs to be angled to avoid sharp changes in impedance. c.3 impedance matching trace impedance should match the impedance of the media as close as possible to avoid signal re?ections. a typical differential impedance for the cable is about 120 w . the impedance of a trace on the pcb is controlled by its height and width, as well as the thickness of the dielectric. the impedance of a trace pair is controlled by the distance between the two traces. c.4 termination and stub length the impedance of the terminator should match that of the cable. terminators need to be placed at the far ends of the cable and as close to the receiver inputs as possible. stub lengths of any device placed
decoupling c-3 along the bus needs to be kept short to avoid impedance mismatches that result in re?ections. the ultra2 scsi standard stipulates that stub lengths for lvd busses should not exceed 0.1 m. additionally differences in stub lengths between req, ack, data and parity signals shall not exceed 1.27 cm. c.5 decoupling decoupling caps need to be as close to the chip v dd pins as possible. the main power supply line should also be decoupled. smt parts are preferred. the long lead lengths of axial leaded parts add inductance to the line. c.6 dielectric another design criteria that should be considered is that the dielectric constant of the board material should be as low as possible. te?on has a dielectric constant rating twice as low as fr-4, which is a common material used in pcbs and so has lower losses. the disadvantage of te?on is that it is more expensive. c.7 considerations speci?c to the SYM53C895 this section discusses speci?c issues that relate to the SYM53C895 device. c.7.1 rbias +/ - pins the rbias +/ - pins, 130 and 129, need to have a 2.2 k w resistor between them to provide the correct bias current to the lvd pads. additionally + 3.3 v needs to be connected to rbias - , pin 129. scsi lines should be short, with no ts and all of them are about the same length. all pci lines need to be less than 1.5 inches long. all gnd and pwr traces need to be short, wide, and doubled.
c-4 circuit board layout issues c.7.2 physical dimensions refer to the mechanical drawing in the data manual for speci?c dimensions. c.7.3 power requirements a 3.3 v regulator (lt1086) derives the v dd supply voltage. c.7.4 v dd-a pin the v dd-a pin (pin 85 or h19) on the SYM53C895 scsi i/o processor (siop) provides power to the phase locked loop (pll) and is sensitive to noise. board con?gurations that expose v dd-a to noise above 90 mv at frequencies above 120 mhz are susceptible. external ac ?ltering is required to prevent high frequency noise from reaching the pll. neglecting to incorporate this ?lter may result in unpredictable scsi bus behavior. this is particularly problematic during scsi data out and data in phases at ultra2 speeds. analog power noise affects the ability of the siop to accurately clock req/ and ack/ signals. as a result, the siop may double clock an incoming req/ signal or generate an extra ack/ signal. this miscounting manifests itself as a data underrun or a data overrun. a ferrite bead is required to perform this ?ltering. the bead should be placed in series between v dd-a and the 3.3 v power supply as follows: the bead should provide between 50 w and 90 w impedance above 120 mhz and should be rated to handle currents up to 25 ma. no decoupling capacitor is needed in this con?guration. c.7.5 terminators unitrode terminators (ucc5630) are recommended. they provide both lvd and single-ended termination, depending on what mode of operation is detected by the diffsens pin. all gnds to the terminators should be short, wide and doubled. reg is tied to ground through ?ve 1 uf caps. + 3.3 v v dd-a
considerations speci?c to the SYM53C895 c-5 c.7.6 capacitive load the total capacitance budget dictated by the scsi parallel interconnect - 2 (spi-2) standard is presently 25 pf. the SYM53C895 is about 13 pf. a high density (68 pin) connector is about 3 pf. that leaves a budget of about 10pf for traces. calculations show that the trace lengths should be held to about 4 inches maximum under these conditions. further calculations to determine allowable deltas in trace length between different signals show that +/ - 1.46 inches is the maximum. this accommodates less than 200 ps of skew between signals. c.7.7 spi-2 document refer to the scsi parallel interconnect 2 (spi-2) standard on ultra2 scsi for speci?c de?nitions of lvd technology as it pertains to scsi. it also talks about requirements for ultra2 scsi data rates, vhdci connectors, sca-2 connectors, diffsens and termpwr signals. the spec, which is up to revision 11, can be found on the lsi logic internet anonymous ftp site: ftp.symbios.com (204.131.200.1) directory: /pub/symchips/scsi
c-6 circuit board layout issues
symbios SYM53C895 pci to ultra2 scsi i/o processor ix-1 index symbols (1b[7:0]) 5-35 (a[6:0]) 6-23 (a7) 6-23 (aap) 5-19 (abrt) 5-38 , 5-46 , 5-63 (ack) 5-36 , 5-37 , 6-20 (adb) 5-20 (adck) 5-56 (adder) 5-66 (aesp) 5-21 (aip) 5-41 (arb1[1:0]) 5-17 (art) 5-81 (atn) 5-36 , 5-37 , 6-20 (aws) 5-84 (baro[31:0]) 5-9 (barz[31:0]) 5-9 (bbck) 5-56 (bc) 6-38 (bdis) 5-54 (bf) 5-38 , 5-63 (bl[1:0]) 5-60 (bl2) 5-57 (bo[7:0]) 5-53 (bo[9:8]) 5-57 (bof) 5-62 (bsbmc) 5-68 (bsrtch) 5-51 (bsy) 5-36 , 5-37 (c/d) 5-36 , 5-37 , 5-43 (cc) 6-20 (cc[23:0]) 5-7 (ccf[2:0]) 5-27 (cd) 6-31 (chm) 5-23 (cio) 5-51 (clf) 5-52 (cls[7:0]) 5-7 (clse) 5-64 (cm) 5-51 (cmp) 5-66 , 5-70 (com) 5-65 (con) 5-21 , 5-48 (cp) 6-31 (csf) 5-87 (ct) 6-30 (d8) 6-22 (dack) 5-51 (dbc) 5-58 (dcm) 6-31 (dcmd) 5-58 (dcv) 6-32 (ddir) 5-50 , 5-57 (df[7:0]) 5-57 (dfe) 5-38 (dfs) 5-56 (dhp) 5-20 (did[15:0]) 5-3 (dif) 5-84 (diom) 5-61 (dip) 5-49 (dm) 5-45 (dnad) 5-59 (dpe) 5-5 (dpr) 5-6 (drd) 5-75 (dreq) 5-51 (dsa) 5-46 , 6-37 (dsi) 5-86 (dsp) 5-59 (dsps) 5-59 (dt[10:9]) 5-6 (dwr) 5-74 (ebm) 5-4 (eis) 5-5 (ems) 5-4 (enc) 5-28 , 5-33 (endid[3:0]) 6-20 (enid) 5-37 (epc) 5-19 (eper) 5-4 (erba[31:0]) 5-12 (erl) 5-61 (ermp) 5-62 (ews) 5-26 (exc) 5-20 (ext) 5-84 (fbl[2:0]) 5-55 (fe) 5-75 (ff[3:0]) 5-42 (ff4) 5-45 (ffl[3:0]) 5-50 (flf) 5-52 (fm) 5-52 (fmt[3:0]) 5-50 (gen) 5-69 , 5-72 (gen[3:0]) 5-79 (gensf) 5-77 (gpio[4:0]) 5-34 (gpio_en) 5-75 , 5-76 (hsc) 5-86
ix-2 index (ht[7:0]) 5-8 (hth) 5-69 , 5-72 (hth[7:4]) 5-76 (hthba) 5-77 (hthsf) 5-79 (i/o) 5-36 , 5-37 , 5-43 (ia) 6-6 (iarb) 5-21 (if) 6-30 (iid) 5-39 , 5-64 (il[7:0]) 5-13 (ilf) 5-40 (immd) 6-23 (intf) 5-48 (ip[7:0]) 5-13 (irqd) 5-65 (irqm) 5-65 (it[1:0]) 6-6 , 6-13 , 6-22 , 6-26 (it[2:0]) 6-34 , 6-37 (jmp) 6-30 (ldsc) 5-45 (lf1) 5-44 (loa) 5-41 (lock) 5-89 (low) 5-85 (ls) 6-37 (lt[7:0]) 5-8 (m/a) 5-66 , 5-70 (man) 5-62 (masr) 5-57 (mdpe) 5-38 , 5-63 (me) 5-75 (mg[7:0]) 5-14 (ml[7:0]) 5-14 (mo[4:0]) 5-31 (mpee) 5-55 (msg) 5-36 , 5-37 , 5-43 (nf) 6-34 , 6-37 (olf) 5-40 (olf1) 5-44 (opc [2:0]) 6-26 (opc) 6-8 (opc[2:0]) 6-13 , 6-22 (oper[2:0]) 6-22 (orf) 5-40 (orf1) 5-44 (par) 5-68 , 5-71 (pfen) 5-64 (pff) 5-64 (pscpt) 5-75 (qen) 5-82 (qsel) 5-82 (ra) 6-17 , 6-29 (ra[6:0]) 6-37 (ramba[31:0]) 5-10 (req) 5-36 , 5-37 (respid0) 5-80 (respid1) 5-80 (rid[7:0]) 5-6 (rma) 5-5 (rof) 5-84 (rre) 5-28 (rsl) 5-67 , 5-70 (rst) 5-21 , 5-67 , 5-71 (rst/) 5-41 (rta) 5-5 (s16) 5-86 (sa) 6-21 (sbdl) 5-89 (sbmc) 5-72 (sce) 5-83 (scf[2:0]) 5-26 (sclk) 5-82 (scpts) 5-75 (scratch a) 5-60 (scratchb) 5-90 (scratchcCscratchj) 5-90 (scsip[2:0]) 6-11 , 6-28 (sdp0/) 5-41 (sdp0l) 5-43 (sdp1) 5-45 (sdu) 5-23 (se) 5-4 (sel) 5-36 , 5-37 , 5-66 , 5-70 (sel) 6-20 (sel[3:0]) 5-77 (sem) 5-47 (sge) 5-67 , 5-70 (sid[15:0]) 5-11 (sidl) 5-88 (sigp) 5-47 , 5-50 (siom) 5-61 (sip) 5-48 (sir) 5-39 , 5-63 (siso) 5-82 (slb) 5-84 (slpar) 5-73 (slphben) 5-24 (slpmd) 5-24 (slt) 5-81 (smode) 5-88 (sodl) 5-89 (som) 5-81 (soz) 5-81 (spl1) 5-45 (sre) 5-28 (srst) 5-47 (srtm) 5-55 (ssaid[3:0]) 5-80 (sse) 5-5 (ssi) 5-39 , 5-63 (ssm) 5-64 (sst) 5-22 (start) 5-18 (std) 5-65 (sto) 5-68 , 5-72 (str) 5-86 (stw) 5-87 (svid[15:0]) 5-10 (swide) 5-74 (szm) 5-84 (tc[23:0]) 6-12 , 6-34 (te) 5-85 (temp) 5-53 (teop) 5-51 (ti) 6-18 (tia) 6-7 (tm) 6-20 (tp[2:0]) 5-29 (trg) 5-19 (ttm) 5-87 (typ[7:4]) 5-74
index ix-3 (udc) 5-67 , 5-71 (ultra) 5-25 (v[3:0]) 5-52 (val) 5-36 (vid[15:0] 5-3 (vue0) 5-24 (vue1) 5-24 (watn) 5-18 (wie) 5-4 (woa) 5-41 (wrie) 5-53 (wsr) 5-25 (wss) 5-24 (wvp) 6-31 (zmod) 5-54 (zsd) 5-55 numerics 16 kbytes interface with 200 ns memory b-1 16-bit system bit 5-86 208-pin qfp 7-63 , 7-66 256 kbytes interface with 150 ns memory b-3 32-bit addressing 6-7 512 kbytes interface with 150 ns memory b-4 64 kbytes interface with 200 ns memory b-2 a abort operation bit 5-46 aborted bit 5-38 , 5-63 absolute maximum stress ratings 7-1 active negation see tolerant technology active termination 2-24 adder register 5-66 adder sum output register 5-66 address and data pins 4-7 always wide scsi bit 5-84 arbitration immediate arbitration bit 5-21 arbitration in progress bit 5-41 arbitration pins 4-9 arbitration priority encoder test bit 5-81 assert even scsi parity bit 5-21 assert satn/ on parity error bit 5-19 assert scsi ack/ signal bit 5-36 assert scsi atn/ signal bit 5-36 assert scsi bsy/ signal bit 5-36 assert scsi c_d/ signal bit 5-36 assert scsi data bus bit 5-20 assert scsi i_o signal bit 5-36 assert scsi msg/ signal bit 5-36 assert scsi req/ signal bit 5-36 assert scsi rst/ signal bit 5-21 assert scsi sel/ signal bit 5-36 asynchronous scsi send 2-3 b back to back read timings 7-30 back to back write timings 7-32 base address one - memory (baro[31:0]) 5-9 base address register zero - i/o (barz[31:0]) 5-9 big and little endian support 2-20 block move instructions 6-6 burst disable bit 5-54 burst length bits 5-57 , 5-60 burst op code fetch enable bit 5-62 burst op code fetch timings 7-28 burst read timings 7-34 burst write timings 7-36 byte count bits 6-38 byte empty in dma fifo bit 5-50 byte full in dma fifo bit 5-50 byte offset counter bits 5-53 , 5-57 c cache line size cls[7:0] 5-7 cache line size enable bit 5-64 cache mode, see pci cache mode 3-4 call instruction 6-27 capacitive load c-5 carry test bit 6-30 chained block moves 2-39 to 2-42 sodl register 2-41 swide register 2-40 wide scsi receive bit 2-40 wide scsi send bit 2-40 chained mode bit 5-23 chip revision level bits 5-52 chip test five register 5-56 chip test four register 5-54 chip test one register 5-50 chip test six register 5-57 chip test three register 5-52 chip test two register 5-50 chip test zero register 5-49 chip type bits 5-74 class code register 5-7 clear dma fifo bit 5-52 clear instruction 6-15 , 6-17 clear scsi fifo bit 5-87 clock address incrementor bit 5-56 clock byte counter bit 5-56 clock conversion factor bits 5-27 clock quadrupler. see scsi clock quadrupler clock timing 7-11 command register 5-3 compare data bit 6-31 compare phase bit 6-31 configuration register read timings 7-16 configuration register write timings 7-17 configuration registers 3-10 configured as i/o bit 5-51 configured as memory bit 5-51 connected bit 5-21 , 5-48 crosstalk problems c-2 ctest0 register 5-49 ctest1 register 5-50 ctest2 register 5-50 ctest3 register 5-52 ctest4 register 5-54 ctest5 register 5-56 ctest6 register 5-57
ix-4 index d data acknowledge status bit 5-51 data compare mask 6-31 data compare value 6-32 data parity error reported (dpr) 5-6 data path 2-3 data read bit 5-75 data request status bit 5-51 data structure address register 5-46 data transfer direction bit 5-50 data write bit 5-74 dbc register 5-58 dcmd register 5-58 dcntl register 5-64 decoupling caps c-3 designing an ultra2 scsi system 2-10 destination address bits 6-23 destination i/o-memory enable bit 5-61 detected parity error (from slave) (dpe) 5-5 device id (did[15:0]) 5-3 devsel/ timing (dt[10:9]) 5-6 dfifo register 5-53 dielectric constant c-3 dien register 5-63 diffsens mismatch bit 5-45 diffsens pin 4-13 diffsens signal 4-11 direct addressing 6-19 disable halt on parity error or atn 5-20 disable single initiator response bit 5-86 disconnect instruction 6-14 dma byte counter register 5-58 dma command register 5-58 dma control register 5-64 dma core 2-2 dma direction bit 5-57 dma fifo 2-3 dma fifo bits 5-57 dma fifo empty bit 5-38 dma fifo register 5-53 dma fifo size bit 5-56 dma interrupt enable register 5-63 dma interrupt pending bit 5-49 dma mode register 5-60 dma next address register 5-59 dma scripts pointer register 5-59 dma scripts pointer save register 5-59 dma status register 5-38 dmode register 5-60 dnad register 5-59 dsa register 5-46 dsa relative 6-37 dsp register 5-59 dsps register 5-59 , 6-35 dstat register 5-38 e enable bus mastering (ebm) 5-4 enable i/o space (eis) 5-5 enable memory space (ems) 5-4 enable parity checking bit 5-19 enable parity error response (eper) 5-4 enable read line bit 5-61 enable read multiple bit 5-62 enable response to reselection bit 5-28 enable response to selection bit 5-28 enable wide scsi bit 5-26 encoded scsi destination id bits 5-33 , 5-37 , 6-20 error reporting pins 4-9 expansion rom base address (erba[31:0]) 5-12 extend sreq/sack filtering bit 5-84 external memory interface 2-11 , 2-12 configuration 2-12 gpio4 bit 5-34 memory sizes supported 2-12 multiple byte accesses 7-14 parallel rom interface 2-11 pin description 4-18 slow memory 2-13 system requirements 2-11 external memory read timings 7-20 external memory write timings 7-23 extra clock cycle of data setup bit 5-20 f fetch enable 5-75 fetch pin mode bit 5-52 fifo byte control bits 5-55 fifo flags bit 4 5-45 fifo flags bits 5-42 first dword 6-6 , 6-13 , 6-22 , 6-26 , 6-34 , 6-37 flush dma fifo bit 5-52 frequency lock 5-89 function complete bit 5-66 , 5-70 g general description 1-1 general purpose pin control register 5-75 general purpose register 5-34 general purpose timer expired bit 5-69 , 5-72 general purpose timer period bits 5-79 general purpose timer scale factor bit 5-77 gpcntl register 5-75 gpio enable 5-75 , 5-76 gpreg register 5-34 h halt scsi clock bit 5-86 handshake to handshake timer bus activity enable bit 5-77 handshake to handshake timer expired bit 5-69 , 5-72 handshake to handshake timer period bit 5-76 header type (ht[7:0]) 5-8 high impedance mode bit 5-54 high voltage differential mode 5-45 autoswitching with lvd and single-ended mode 2-16 description 2-16 fast scsi timings 7-55 scsi-1 timings 7-54 high voltage differential transfers 20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers) 80 mhz clock 7-58 high voltage diffferential mode scsi pin description 4-14
index ix-5 i i/o instructions 6-13 illegal instruction detected bit 5-39 , 5-64 immediate data bits 6-23 impedance of the terminator c-2 indirect addressing bit 6-6 initiator asynchronous receive timing 7-52 initiator asynchronous send timing 7-51 initiator mode 6-16 instruction prefetching 2-8 prefetch enable bit 5-64 prefetch flush bit 5-64 prefetch unit flushing 2-9 instruction type bits 6-37 instruction type-block move 6-6 instruction type-i/o instruction bits 6-13 instruction type-memory move bits 6-34 instruction type-read/write instruction 6-22 instruction type-transfer control instruction bits 6-26 interface control pins 4-8 internal ram, see scripts ram interrupt instruction 6-28 interrupt line 5-13 interrupt on the fly bit 5-48 , 6-30 interrupt on the fly instruction 6-28 interrupt pin (ip[7:0]) 5-13 interrupt status register 5-46 interrupts 2-32 fatal vs. nonfatal interrupts 2-34 halting 2-37 irq disable bit 2-34 masking 2-35 sample service routine 2-38 stacked interrupts 2-36 interrupts output timings 7-14 irq disable bit 5-65 irq mode bit 5-65 istat register 5-46 j jump address bits 6-32 jump call a relative address 6-29 jump call an absolute address 6-29 jump if true/false bit 6-30 jump instruction 6-27 l last disconnect bit 5-45 latched scsi parity bit 5-43 latched scsi parity for sd[15:8] bit 5-45 latency timer (lt[7:0]) 5-8 load/store bit 6-37 lost arbitration bit 5-41 low voltage differential. see lvd link lvd link benefits 1-3 dc characteristics 7-2 diffsens pin 4-11 operation 2-16 scsi bus mode change bit 5-68 , 5-72 scsi mode bit 5-88 scsi pin descriptions 4-10 m macntl register 5-74 manual start mode bit 5-62 master control for set or reset pulses bit 5-57 master data parity error bit 5-38 , 5-63 master enable bit 5-75 master parity error enable bit 5-55 max scsi synchronous offset bits 5-31 max_lat (ml[7:0]) 5-14 mechanical drawing 7-66 memory access control register 5-74 memory i/o address/dsa offset bits 6-38 memory move instructions 6-33 and scripts instruction prefetching 2-9 no flush option 2-9 memory read line command 3-8 memory read multiple command 3-9 memory write and invalidate command 3-6 min_gnt (mg[7:0]) 5-14 move to/from sfbr cycles 6-24 n new features 1-2 no flush bit 6-34 no flush store instruction only bit 6-37 normal/fast memory ( 3 128 kbytes), multiple byte access read cycle 7-42 write cycle 7-44 o op code bits 6-8 , 6-13 , 6-22 , 6-26 op code fetch bursting 2-9 op code fetch, nonburst timings 7-26 operating conditions 7-2 operating register/scripts ram read timing 7-18 operating register/scripts ram write timings 7-19 operating registers adder sum output 5-66 chip test five 5-56 chip test four 5-54 chip test one 5-50 chip test six 5-57 chip test three 5-52 chip test two 5-50 chip test zero 5-49 data structure address 5-46 dma byte counter 5-58 dma command 5-58 dma control 5-64 dma fifo 5-53 dma interrupt enable 5-63 dma mode 5-60 dma next address 5-59 dma scripts pointer 5-59 dma scripts pointer save 5-59 dma status 5-38 general information 5-1 general purpose 5-34 general purpose pin control 5-75 interrupt status 5-46 memory access control 5-74 response id one 5-80
ix-6 index response id zero 5-80 scratch byte 5-64 scratch register a 5-60 scratch register b 5-90 scratch registers c-j 5-90 scsi bus data lines 5-89 scsi chip id 5-28 scsi control one register 5-20 scsi control three 5-25 scsi control two register 5-23 scsi control zero 5-17 scsi destination id 5-33 scsi first byte received 5-35 scsi input data latch 5-88 scsi interrupt enable one 5-68 scsi interrupt enable zero 5-66 scsi interrupt status one 5-72 scsi interrupt status zero 5-69 scsi longitudinal parity 5-73 scsi output control latch 5-36 scsi output data latch 5-89 scsi selector id 5-36 scsi status one 5-42 scsi status two 5-44 scsi status zero 5-40 scsi test four 5-88 scsi test one 5-82 scsi test three 5-85 scsi test two 5-83 scsi test zero 5-80 scsi timer one 5-77 scsi timer zero 5-76 scsi transfer 5-29 scsi wide residue 5-74 temporary stack 5-53 operator bits 6-22 p parity 2-22 to 2-24 parity error bit 5-71 pci cache mode 3-4 cache line size enable bit 5-64 enable read multiple bit 5-62 memory read line command 3-8 memory read multiple command 3-9 memory write and invalidate command 3-6 write and invalidate enable bit 5-53 pci commands 3-2 pci configuration registers base address one 5-9 base address zero 5-9 cache line size 5-7 class code 5-7 command 5-3 device id 5-3 expansion rom base address 5-12 header type 5-8 interrupt line 5-13 interrupt pin 5-13 latency timer 5-8 max_lat 5-14 min_gnt 5-14 ram base address 5-10 revision id 5-6 status 5-5 subsystem id 5-11 subsystem vendor id 5-10 vendor id 5-3 pci configuration space 3-1 pci i/o space 3-2 pci memory space 3-2 phase mismatch bit 5-70 pin diagram 7-63 pins additional pins 4-16 address and data pins 4-7 arbitration pins 4-9 error reporting pins 4-9 external memory interface 4-18 interface control pins 4-8 power and ground 4-5 scsi pins high voltage differential mode 4-14 lvd link 4-10 single-ended mode 4-12 system pins 4-7 pointer scripts bit 5-75 prefetch enable bit 5-64 prefetch flush bit 2-9 , 5-64 pull-ups, internal 4-4 q quadrupling the scsi clock frequency 5-83 r ram base address (ramba[31:0]) 5-10 ram, see scripts ram rbias +/- pins c-3 read cycle timings, 64 kbytes rom 7-49 read cycle timings, normal/fast memory ( 3 128 kbytes), single byte access 7-38 read cycle timings, slow memory ( 3 128 kbytes) 7-46 read/write instructions 6-22 , 6-24 read/write system memory from a script 6-34 read-modify-write cycles 6-23 received master abort (from master) (rma) 5-5 received target abort (from master) (rta) 5-5 register address - a[6:0] 6-23 register address bits 6-37 register bits scsi msg/ signal 5-43 register map a-1 pci registers a-1 scsi registers a-2 relative addressing 6-19 relative addressing mode bit 6-17 , 6-29 reselect instruction 6-14 reselected bit 5-67 , 5-70 reset input timing 7-13 reset scsi offset bit 5-84 respid0 register 5-80 respid1 register 5-80 response id one register 5-80 response id zero register 5-80 return instruction 6-27 revision id (rid[7:0]) 5-6 revision id register 5-6 revision level bits 5-52 routing of differential lines c-2
index ix-7 s sack/ status bit 5-37 satn/ active bit 5-70 satn/ status bit 5-37 sbdl register 5-89 sbr register 5-64 sbsy status bit 5-37 sc_d/ status bit 5-37 scid register 5-28 sclk bit 5-82 sclk quadrupler enable 5-82 sclk quadrupler select 5-82 scntl0 register 5-17 scntl1 register 5-20 scntl2 register 5-23 scntl3 register 5-25 scratch register 5-64 scratcha register 5-60 scratcha/b operation bit 5-51 scratchb register 5-90 scripts bit 5-75 scripts interrupt instruction received 5-39 , 5-63 scripts processor 2-7 instruction prefetching 2-8 internal ram for instruction storage 2-8 performance 2-7 scripts ram 2-8 scratcha/b operation bit 5-51 scsi core 2-2 lvd link 2-16 termination 2-24 tolerant technology 1-4 ultra2 2-10 scsi atn condition bit 5-66 scsi bus data lines register 5-89 scsi bus interface 2-15 to 2-28 scsi bus mode change bit 5-68 , 5-72 scsi c_d/ signal bit 5-43 scsi chip id register 5-28 scsi clk frequency quadrupling 5-83 scsi clock quadrupler 5-82 frequency lock bit 5-89 scsi clock rates 5-26 scsi control enable bit 5-83 scsi control one register 5-20 scsi control three register 5-25 scsi control two register 5-23 scsi core 2-2 scsi data high impedance bit 5-55 scsi destination id register 5-33 scsi differential mode bit 5-84 scsi disconnect unexpected bit 5-23 scsi encoded destination id 6-20 scsi fifo test read bit 5-86 scsi fifo test write bit 5-87 scsi first byte received register 5-35 scsi gross error bit 5-67 , 5-70 scsi high-impedance mode bit 5-84 scsi i/o instructions 6-13 scsi i_o/ signal bit 5-43 scsi input data latch register 5-88 scsi instructions block move 6-6 read/write 6-22 scsi interrupt enable one register 5-68 scsi interrupt enable zero register 5-66 scsi interrupt pending bit 5-48 scsi interrupt status one register 5-72 scsi interrupt status zero register 5-69 scsi isolation mode bits 5-82 scsi longitudinal parity register 5-73 scsi loopback mode bit 5-84 scsi low level mode bit 5-85 scsi mode bit 5-88 scsi msg/ signal bit 5-43 scsi output control latch register 5-36 scsi output data latch register 5-89 scsi parity error bit 5-68 scsi phase bits 6-11 , 6-28 scsi phase mismatch bit 5-66 scsi pins 4-10 , 4-12 scsi reset condition bit 5-67 scsi rst/ received bit 5-71 scsi rst/ signal bit 5-41 scsi scripts operation 6-2 sample instruction 6-3 scsi sdp0/ parity signal bit 5-41 scsi sdp1 signal bit 5-45 scsi selected as id bits 5-80 scsi selector id register 5-36 scsi status one register 5-42 scsi status two register 5-44 scsi status zero register 5-40 scsi synchronous offset maximun 5-81 scsi synchronous offset zero bit 5-81 scsi synchronous transfer period bits 5-29 scsi test one register 5-82 scsi test three register 5-85 scsi test two register 5-83 scsi test zero register 5-80 scsi timer one register 5-77 scsi timer zero register 5-76 scsi timings 7-51 to 7-59 scsi transfer register 5-29 scsi true end of process bit 5-51 scsi valid bit 5-36 scsi wide residue register 5-74 scsi-1 transfers (differential, 4.17 mbytes/s) timing 7-54 (single-ended, 5.0 mbytes/s) timing 7-54 scsi-2 fast transfers 10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers) 40 mhz clock timing 7-55 50 mhz clock timing 7-56 sdid register 5-33 second dword 6-12 , 6-21 , 6-23 , 6-32 , 6-35 , 6-38 select instruction 6-16 select with atn/ bit 6-20 select with satn/ on a start sequence 5-18 selected bit 5-66 , 5-70 selection or reselection timeout bit 5-68 , 5-72 selection response logic test bits 5-81 selection timeout 5-77 semaphore bit 5-47 serr/ enable (se) 5-4 set instruction 6-15 , 6-17 set/clear carry bit 6-20 set/clear sack/ bit 6-20 set/clear satn/ bit 6-20 set/clear target mode bit 6-20
ix-8 index sfbr register 5-35 shadow register test mode bit 5-55 si_o/ status bit 5-37 sidl least significant byte full bit 5-40 sidl most significant byte full 5-44 sidl register 5-88 sien0 register 5-66 sien1 register 5-68 signal name alphabetical 7-65 bga position 7-61 pin number 7-64 signal process 5-47 , 5-50 signaled system error (sse) 5-5 sigp bit 5-47 , 5-50 single-ended mode scsi pin description 4-12 single-step interrupt bit 5-39 , 5-63 single-step mode bit 5-64 sist0 register 5-69 sist1 register 5-72 slpar high byte enable 5-24 slpar mode bit 5-24 slpar register 5-73 smsg/ status bit 5-37 socl least significant byte full bit 5-40 socl register 5-36 sodl most significant byte full bit 5-44 sodl register 5-89 sodr least significant byte full bit 5-40 sodr most significant byte full bit 5-44 software reset bit 5-47 source i/o-memory enable bit 5-61 sreq/ status bit 5-37 ssel/ status bit 5-37 ssid register 5-36 sstat0 register 5-40 sstat1 register 5-42 sstat2 register 5-44 stacked interrupts 2-36 start address bits 6-12 , 6-21 start dma operation bit 5-65 start scsi transfer 5-22 start sequence 5-18 status register 5-5 stest0 register 5-80 stest1 register 5-82 stest2 register 5-83 stest3 register 5-85 stime0 register 5-76 stime1 register 5-77 store instructions prefetch unit and 2-9 subsystem id (sid[15:0]) 5-11 subsystem vendor id (svid[15:0]) 5-10 swide register 5-74 sxfer register 5-29 sym53c700 compatibility bit 5-65 SYM53C895 new features 1-2 register map a-1 synchronous clock conversion factor bits 5-26 synchronous data transfer rates 2-29 synchronous scsi send 2-3 system pins 4-7 t table indirect addressing 6-19 table indirect bit 6-7 table indirect mode bit 6-18 table relative addressing 6-19 target asynchronous send timing 7-52 target mode 6-14 target mode bit 5-19 , 6-9 temp register 5-53 , 6-35 , 6-38 temporary register 5-53 termination 2-24 third dword 6-35 , 6-38 timer test mode bit 5-87 timings clock 7-11 interrupt output 7-14 reset input 7-13 scsi 7-51 ultra2 scsi 7-57 tolerant enable bit 5-85 tolerant technology 1-4 benefits 1-5 electrical characteristics 7-8 extend sreq/sack filtering bit 5-84 tolerant enable bit 5-85 trace impedance c-2 transfer control instructions 2-9 , 6-26 transfer counter bits 6-12 , 6-34 transfer rate synchronous 2-29 synchronous clock conversion factor bits 5-26 ttl/cmos signals c-2 u ultra scsi 7-58 ultra scsi single-ended transfers 20.0 mbytes/s (8-bit transfers) or 40.0 mbytes/s (16-bit transfers), quadrupled 40 mhz clock 7-57 ultra2 scsi 2-10 benefits 1-4 lvd link 2-16 synchronous clock conversion factor bits 5-26 ultra2 scsi timings 7-57 ultra2 scsi transfers 40.0 mbytes/s (8-bit transfers) or 80.0 mbytes/s (16-bit transfers) quadrupled 40 mhz clock timing 7-59 unexpected disconnect bit 5-67 , 5-71 unitrode terminator c-4 upper register address line (a7) bit 6-23 use data8/sfbr bit 6-22 v vdd-a pin c-4 vendor id (vid[15:0]) 5-3 vendor unique enhancements 1 bit 5-24 w wait disconnect instruction 6-16 wait for valid phase bit 6-31 wait reselect instruction 6-17 wait select instruction 6-15
index ix-9 watn/ bit 5-18 wide scsi always wide scsi bit 5-84 chained block moves 2-39 swide register 5-74 wide scsi receive bit 5-25 wide scsi send bit 5-24 won arbitration bit 5-41 write and invalidate enable (wie) 5-4 write and invalidate enable bit 5-53 write cycle timings, 64 kbytes rom 7-50 write cycle timings, normal/fast memory ( 3 128 kbytes), sin- gle byte access 7-40 write cycle timings, slow memory ( 3 128 kbytes) 7-47 write/read instructions 6-22 write/read system memory from a script 6-34
ix-10 index
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u.s. distributors by state a. e. avnet electronics http://www.hh.avnet.com b. m. bell microproducts, inc. (for habs) http://www.bellmicro.com i. e. insight electronics http://www.insight-electronics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arkansas w. e. tel: 972.235.9953 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 tempe i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 california agoura hills b. m. tel: 818.865.0266 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 818.594.0404 westlake village i. e. tel: 818.707.2101 colorado denver a. e. tel: 303.790.1662 b. m. tel: 303.846.3065 w. e. tel: 800.933.9953 englewood i. e. tel: 303.649.1800 connecticut cheshire a. e. tel: 203.271.5700 i. e. tel: 203.272.5843 wallingford w. e. tel: 800.605.9953 delaware north/south a. e. tel: 800.526.4812 tel: 800.638.5988 b. m. tel: 302.328.8968 w. e. tel: 856.439.9110 florida altamonte springs b. m. tel: 407.682.1199 i. e. tel: 407.834.6310 boca raton i. e. tel: 561.997.2540 clearwater i. e. tel: 727.524.8850 fort lauderdale a. e. tel: 954.484.5482 w. e. tel: 800.568.9953 miami b. m. tel: 305.477.6406 orlando a. e. tel: 407.657.3300 w. e. tel: 407.740.7450 tampa w. e. tel: 800.395.9953 st. petersburg a. e. tel: 727.507.5000 georgia atlanta a. e. tel: 770.623.4400 b. m. tel: 770.980.4922 w. e. tel: 800.876.9953 duluth i. e. tel: 678.584.0812 hawaii a. e. tel: 800.851.2282 idaho a. e. tel: 801.365.3800 w. e. tel: 801.974.9953 illinois north/south a. e. tel: 847.797.7300 tel: 314.291.5350 chicago b. m. tel: 847.413.8530 w. e. tel: 800.853.9953 schaumburg i. e. tel: 847.885.9700 indiana fort wayne i. e. tel: 219.436.4250 w. e. tel: 888.358.9953 indianapolis a. e. tel: 317.575.3500 iowa w. e. tel: 612.853.2280 cedar rapids a. e. tel: 319.393.0033 kansas w. e. tel: 303.457.9953 kansas city a. e. tel: 913.663.7900 lenexa i. e. tel: 913.492.0408 kentucky w. e. tel: 937.436.9953 central/northern/ western a. e. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana w. e. tel: 713.854.9953 north/south a. e. tel: 800.231.0253 tel: 800.231.5575 maine a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 maryland baltimore a. e. tel: 410.720.3400 w. e. tel: 800.863.9953 columbia b. m. tel: 800.673.7461 i. e. tel: 410.381.3131 massachusetts boston a. e. tel: 978.532.9808 w. e. tel: 800.444.9953 burlingtonr i. e. tel: 781.270.9400 marlborough b. m. tel: 508.480.9099 woburn b. m. tel: 781.933.9010 michigan brighton i. e. tel: 810.229.7710 detroit a. e. tel: 734.416.5800 w. e. tel: 888.318.9953 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 609.222.9566 pine brook w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119
u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tulsa a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beavertonr b. m. tel: 503.524.0787 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 philadelphia a. e. tel: 800.526.4812 b. m. tel: 215.741.4080 w. e. tel: 800.871.9953 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 washington kirkland i. e. tel: 425.820.8100 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953
direct sales representatives by state (component and hab) e. a. earle associates e. l. electrodyne - ut grp group 2000 i. s. in?nity sales, inc. ion ion associates, inc. r. a. rathsburg associ- ates, inc. sgy synergy associates, inc. arizona tempe e. a. tel: 480.921.3305 california calabasas i. s. tel: 818.880.6480 irvine i. s. tel: 714.833.0300 san diego e. a. tel: 619.278.5441 illinois elmhurst r. a. tel: 630.516.8400 indiana cicero r. a. tel: 317.984.8608 ligonier r. a. tel: 219.894.3184 plain?eld r. a. tel: 317.838.0360 massachusetts burlington sgy tel: 781.238.0870 michigan byron center r. a. tel: 616.554.1460 good rich r. a. tel: 810.636.6060 novi r. a. tel: 810.615.4000 north carolina cary grp tel: 919.481.1530 ohio columbus r. a. tel: 614.457.2242 dayton r. a. tel: 513.291.4001 independence r. a. tel: 216.447.8825 pennsylvania somerset r. a. tel: 814.445.6976 texas austin ion tel: 512.794.9006 arlington ion tel: 817.695.8000 houston ion tel: 281.376.2000 utah salt lake city e. l. tel: 801.264.8050 wisconsin muskego r. a. tel: 414.679.8250 saukville r. a. tel: 414.268.1152
sales of?ces and design resource centers lsi logic corporation corporate headquarters tel: 408.433.8000 fax: 408.433.8989 north america california costa mesa - mint technology tel: 949.752.6468 fax: 949.752.6868 irvine tel: 949.809.4600 fax: 949.809.4444 pleasanton design center tel: 925.730.8800 fax: 925.730.8700 san diego tel: 858.467.6981 fax: 858.496.0548 silicon valley tel: 408.433.8000 fax: 408.954.3353 wireless design center tel: 858.350.5560 fax: 858.350.0171 colorado boulder tel: 303.447.3800 fax: 303.541.0641 colorado springs tel: 719.533.7000 fax: 719.533.7020 fort collins tel: 970.223.5100 fax: 970.206.5549 florida boca raton tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green tel: 270.793.0010 fax: 270.793.0040 maryland bethesda tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis tel: 612.921.8300 fax: 612.921.8399 new jersey red bank tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology tel: 609.489.5530 fax: 609.489.5531 new york fairport tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh tel: 919.785.4520 fax: 919.783.8909 oregon beaverton tel: 503.645.0589 fax: 503.645.6612 texas austin tel: 512.388.7294 fax: 512.388.4171 plano tel: 972.244.5000 fax: 972.244.5001 houston tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milano lsi logic s.p.a. tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka tel: 81.6.947.5281 fax: 81.6.947.5287 korea seoul lsi logic corporation of korea ltd tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd tel: 65.334.9061 fax: 65.334.4749 tel: 65.835.5040 fax: 65.732.5047 sweden stockholm lsi logic ab tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan taipei lsi logic asia, inc. taiwan branch tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers
international distributors australia new south wales reptechnic pty ltd tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. tel: 86.10.6804.2534 fax: 86.10.6804.2521 france rungis cedex azzurri technology france tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd tel: 852.2428.0008 fax: 852.2401.2105 eastele tel: 852.2798.8860 fax: 852.2305.0640 india bangalore spike technologies india private ltd tel: 91.80.664.5530 fax: 91.80.664.9748 israel tel aviv eastronics ltd tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo global electronics corporation tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 yokohama-city macnica corporation tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag tel: 41.32.3743232 fax: 41.32.3743233 taiwan taipei avnet-mercuries corporation, ltd tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd tel: 886.2.2721.9533 fax: 886.2.2773.3756 serial semiconductor corporation, ltd tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd tel: 44.1628.826826 fax: 44.1628.829730 swindon ebv elektronik tel: 44.1793.849933 fax: 44.1793.859555 sales of?ces with design resource centers

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